مجله مهندسی برق و الکترونیک ایران
سال چهاردهم شماره 2 (تابستان 1396)

In this paper, a more realistic cognitive radio network is proposed which considers several secondary links, some secondary relays, and one primary link. In the network, there are two steps of transmission from secondary sources to secondary destinations. At the first step, when primary link is idle, all of the secondary sources simultaneously broadcast their information to the relays. At the second step, the relays that successfully decode the information employ a new cooperative beamforming method and forward them to the secondary destination without causing harmful interference to the primary destination irrespective of whether primary link is idle or not. It is assumed that the channel state information between relays and primary destination isn’t perfectly known at the relays and they have erroneous estimation of the channel. The proposed cooperative beamforming method can maximize the received signal power at the secondary destination subject to keep received interference plus noise power at the primary destination under the predefined threshold. Results of simulations confirm validity of the method and improved performance compared to Zero-Forcing beamforming. The proposed cooperative beamforming can remain the interference plus noise power at the primary destination below the threshold even if the error in channel estimation is maximum.

In this paper, power efficiency (PE) of a relay interference channel including multiple transmitter nodes, multiple relay nodes and multiple destination is investigated. It is assumed that the destination and transmitter nodes are equipped with a few number of antennas but the relay nodes have a large number of antennas. Amplify-forward and decode-forward schemes by using MRT/MRC and ZF processes are considered. The PE of the system is studied and the effect of the transmitter and relay nodes power on the PE is investigated. It will be shown that by using a large number of antennas at the relay nodes, one can reduce the transmitted power of transmitter nodes without any degradation in the performance. Also, when the relay nodes have a limited number antennas, decode-forward scheme has better performance with respect to amplify-forward scheme. However, by increasing the number of relays antennas they are converge to each other. Finally, it is shown that the decode-forward scheme needs less power for achieving 1 bit/s.

Wireless sensor networks (WSN) is presented solution for the problem of low-cost and flexible monitoring event, especially in places with limited access or dangerous for humans. Wireless sensor networks are built from wireless devices with limited resources thus to Long-Term survival of the Network must use energy-efficient mechanisms, algorithms and protocols. one of the mechanisms controlling the topology (TC), which is composed of two parts, a topology construction and topology maintenance.This paper introduces the new algorithm for energy aware topology construction based on connected dominating set, namely, algorithm EA-CDS, wich is a simple mechanism to build the distributed, energy-efficient topology, that finds optimal connected subset and removes unnecessary nodes with minimum power consumption while the network remains connected and coverage is complete.also ,to maintain network connectivity and unfailing the nodes energy that are constantly located at sending packets path along with it , the DGTERec topology maintenance algorithm is used to balance energy consumption in nodes .Evaluation results show that the EA-CDS protocol for increasing the useful lifetime of the network (Postponing the first node death) and the number of messages sent over the same two protocols (EECDS and CDS-RULE-K) has obvious advantages.
To ensure that the results of Atarraya are acceptable,The performance of the proposed method is evaluated with MATLAB and output results analysis, confirmed the results of the ATARRAYA simulator.

This paper deals with Direction of Arrival (DOA) Estimation using Uniform linear array (ULA) for the case of more sources than sensors in the array processing. Khatri-Rao subspace approach, introduced for DOA estimation for this, in non-stationary signal model. The technique will be shown to be capable to handle stationary signals, too. Identifiability conditions of this approach are addressed. The Cramer-Rao Bound (CRB) is derived for the superior setting and the statistical performance of the estimation method is compared with CRB. Simulations show that the mean-squared error performance of Khatri-Rao approach is within 3 dB of the CRB.

In this paper, new method for reduction of Specific Absorption Rate (SAR) in mobile handset is presented. The idea is based on the array antenna theory and this caused that by improvement of the gain, SNR be preserved and instead of one antenna and one strong hotspot, have the two antenna with two weak hotspot. For this array, the antenna must be equal with similar pattern to have the best array factor (AF). In the other hand in the array mode, the SNR and pattern must be same in comparison of one antenna mode. Finally, by this technique, the SAR %75 and %92 reduced in each antenna and MIMO antenna mode, respectively. Furthermore, this method is compared with EBG method and it has been shown that this method is better.

In this paper, a compact microstrip resonant cell is proposed. Designed based on the hairpin structure, the proposed resonator provides wide stop-band and sharp skirt for low-pass filters. By cascading two of these resonators, a microstrip low-pass filter with cut-off frequency of 1.69GHz is designed and fabricated. According to experimental results, this filter has a small normalized circuit size (0.0108), low insertion loss (less than 0.2dB), wide stop-band from 1.78GHz to 10GHz defined by -20dB attenuation level, and sharp roll-off (308dB/GHz).

We use a multilayer back propagation neural network whose training is based on Levenberg-Marquardt optimization method and apply polyphase codes to its input layer for radar pulse compression in environments with similar targets. The advantage of using polyphase codes (in contrast to binary codes) is lower sidelobe levels and much better Doppler tolerance. The use of Levenberg-Marquardt optimization method in our scheme significantly increases the speed of convergence. The results indicated that after 100 iterations, the main sidelobe for P3 code (N=30) is reduced to -238.66 dB and for P4 code (N=45), it is reduced to -240.51 dB. Besides, the proposed method is robust against noise and shows much higher Doppler tolerance.

In this article, the design and modeling details of room-temperature analog-to-digital converter (ADC) based on silicon quantum-dot (QD) single-electron transistors (SETs) is presented. In contrast to the conventional metal quantum dots, the use of silicon QDs in the scales of few nano-meters enhances the device operation and makes stable the Coulomb blockade and Coulomb oscillation regimes at room temperature. Nano-scale silicon QD-based SETs are also compatible with CMOS fabrication steps and can be integrated along with CMOS circuits on a same substrate. The proposed ADC in this article benefits from stable Coulomb oscillations of silicon QD-based SETs at room temperature. A 3-bit 5-GS/s prototype of this ADC contains three complementary SET pairs and four capacitors in the form of capacitor divider. Simulation results based on Monte-Carlo SIMON simulator demonstrates reliable static and dynamic performance at room temperature.

In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in the circuit is based on Aperture Phase Detection (APD) method. In addition, the proposed charge pump reduces reference spur. The proposed structure of the frequency locked loop reduces the locking time. To evaluate the proposed approch, we simulated the designed PLL using the foundry design kit for 0.18μm CMOS technology. The spur level and lock time of the proposed circuit is -74dBc and 1.9 μs, respectively, implying 5dB improvement in spur level and 32% improvement in lock time compared with the previously proposed circuits. The power consumption of the proposed circuit is 4.15 mW.

Low power single-ended operational amplifier with high slow rate in new technologies due to decreasing dimensionality and supply voltage level has attracted many researchers in recent years. These researchers often used auxiliary circuit for increasing the charging and discharging currents of load and compensation capacitances. Nevertheless, many of these methods are not able to improve the positive and negative slew rates symmetrically, and usually lead to increase power consumption and circuit dimensionality and complexity. Therefore, in this research, an auxiliary circuit in TSMC 0.18 µm technology is provided for improving the slow rate in two-stage operational amplifier with single-ended output. This proposed circuit under a 2 pF load capacitance and a 1.8 V supply voltage could increase the positive and negative slew rates to up 8.87 and 22.67 times, respectively, which lead to significant symmetry in the positive and negative slew rates. Besides, this auxiliary circuit had not significant effects on the gain, bandwidth, unity gain frequency and phase margin of operational amplifier, and only increased the power consumption by as much as 1.5% (10.59 µW). Therefore, this circuit can be a good suggestion to improve slew-rate parameter in the low power operational amplifiers with single-ended output.

Voltage references are crucial part of every circuit, providing a fixed voltage regardless of environmental parameters and device loading. Among several approaches proposed for designing voltage references, bandgap voltage references are the most common, but the bandgap voltage reference is bipolar in nature and does not show good stability when the supply voltage is small. Thus according to the increasing need for voltage references with low power consumption and low power supply, a voltage reference using threshold voltage difference between a native and a typical MOSFET transistor is proposed in this work. Using simulation for 0.18 CMOS technology, temperature coefficient and line sensitivity was measured 15ppm/°Cand0.98%/V respectively. The simulation is done to find the Sensitivity of output voltage to temperature and supply voltage in different biases. Minimum voltage supply for this work is 0.7 v and power consumption at room temperature is 700 nanowatt that make this voltage reference suitable for low power, low voltage circuits, for example nanowatt medical applications. At the end to minimize process variations a digital trimming after process is proposed, where transistors are turned on by controlling signals to have different length and width after fabrication process and different output voltages is simulated by having control switches on or off.

Car license plate detection has been always a challenging task in the context of traffic control and traffic offenses. In this paper, the problem of license plate detection from gray scale images taken in natural conditions is addressed. Our car plate database consists of images with severe imaging conditions such as low quality images, far distanced cameras, and severe weather conditions. The main proposed idea in this paper, is to learn discriminative dictionaries from plate and non-plate exemplars for the classification task. A well-known dictionary learning algorithm is employed for this purpose. However, initial preprocessing techniques for image enhancement are also applied. The achieved results reveal that sparse representation-based techniques in the proposed method can increase the detection accuracy and improve the previously reported results.