Majlesi Journal of Telecommunication Devices
Volume:7 Issue: 4, Dec 2018

Today, reduction of losses and operational costs is considered an important issue in power systems. Demand response program causes diminished consumption during peak hours and thus increased reliability and reduced costs. Reconfiguration of distribution networks are among the practical methods in reducing losses and costs as well as improving the voltage profile. In this paper, the reconfiguration of distribution networks is performed considering demand response potential and in the presence of distribution generated (DG) sources using a new optimization algorithm called mine blast optimization algorithm (MBA). For this purpose, reducing losses, improving voltage profile, and lowering operational costs of the network are also taken into account as objective function. The proposed method is applied on 33-bus radial network. Simulation has been performed using MATLAB software.

In this paper, an operational transconductance amplifier (OTA) is designed, simulated and configured so that input dynamic range is improved by bulk-driven technique of the input transistors. The bulk-driven structure is used in the proposed OTA to stabilize the transconductance and to achieve a high linearity. By changing the control voltage and the input common-mode voltage, the voltages and currents of the circuit are changed so that the transconductance and the voltage gain are changed linearly. Also, setting a reference voltage in the circuit can greatly reduce the destructive effects of undesired changes in the circuit operation during fabrication process. The proposed OTA is designed in 180 nm CMOS technology and required only 0.5 V supply voltage. The simulation results show the OTA voltage gain is varied from 0 dB to 14.2 dB by changing the control voltage from 0 to 0.5 V. Moreover, the input common-mode voltage of the OTA can be changed in the range of 0.125 to 0.375V and without linear degradation. The proposed OTA is dissipated 250 nW and makes it suitable for low-power applications.

In this paper design and simulation of an improved depletion-mode n-channel nanoelectromechanical field effect transistor (NEMFET) at 300K is reported. The designed NEMFET is based on NEMS technology and fully compatible with CMOS fabrication process. A NEMFET is composed of a NEM relay and a MOSFET and comprises a movable gate and a semiconductor part, so that the flowing current is always in the semiconductor part. The nanomechanical movable gate was a bossed doubly clamped beam and simulated by COMSOL Multiphysics software and the electrical part was designed and simulated by ATLAS software. The designed NEMFET had a 25 nm length, 100 nm width and 5.2 nm thicknesses. Optimization was done by applying two 8.5 nm spaces, one between source to gate and the other between gate to drain. Simulation results show in the proposed structure, sub-threshold swing was decreased to 86 mV/dec and the Ion/Ioff ratio was increased to 8.68×104

Lent has created QCA nanoscale devices by merging the cellular automata and quantum electronics. These devices are capable of achieving very high switching speeds and very low electrical power consumption. AES block cipher is now used worldwide. This algorithm is based on the Rijndael cipher which was submitted as a proposal to NIST during the AES selection process. The implementation of this cryptographic algorithm in QCA technology is presented in this paper. On the other hand, the QCADesigner software which is used to simulate QCA circuits is sensitive to the QCA cell count, inputs and outputs. It seems that by increasing the QCA cell count, inputs and outputs, the simulation time will increase and sometimes the simulation will be impossible. A higher level modeling of QCA circuits by VHDL hardware description language and simulation of these models by ModelSim software is presented in this paper to solve the mentioned problem. It is shown that the QCA implementation of the AES algorithm with key, input and output length of 128 bits is easily modeled and simulated in ModelSim software. The implementation results of various implementation methods are also compared in this paper for AES algorithm. It is illustrated that the QCA implementation of this algorithm is the most efficient implementation among existing methods.

This paper, describes a CMOS trans-impedance amplifier (TIA) and Limiting Amplifier (LA) for 2.5Gb/s, low-power opto-electronic communication receiver systems. The single ended TIA, which benefits form active type of inductors, is designed and simulated using 0.18µm CMOS process parameters. The proposed circuits are analyzed mathematically and all necessary simulations for proving the proper performance of the proposed TIA stage and the proposed LA stage such as eye-diagram, MONTECARLO and noise analysis are done. Simulation results in HSPICE show the trans-impedance gain of 45.5dBΩ, frequency bandwidth of 1.85GHz and power consumption of 1.1mW at 1.5V supply for the TIA stage and 87dB gain and 2GHz frequency bandwidth for the whole receiver system, which consumes only 7.3mW power. Results indicate that the proposed circuits are suitable to work as a low-power building block as opto-electrical communication receiver.

Cognitive Radio (CR) technology has been suggested as a solution to the serious problem of spectrum scarcity in recent years. Cooperative Spectrum Sensing (CSS) is the key function to overcome the destructive effect of hidden station, multipath fading and shadowing problems. As many previous studies have shown, the trustworthiness of the CSS can be strictly degraded under Spectrum Sensing Data Falsification (SSDF) attack. In this paper, we introduce an important dynamic fusion rule called Software-Defined CSS (SD-CSS). The main contribution is to analyze the SSDF attack strategy against the CR network and apply the best fusion rule to increase the cooperative sensing performance. Two important SSDF attack parameters, attack strategy and attack ratio, are estimated and the obtained parameters are then used to choose an appropriate fusion rule to improve the CSS performance. The obtained results confirm considerable improvement in correct sensing ratio in massive attack.

A network on the chip is a solution to connection problems compared with traditional-based chip which can fulfil multi-dimensional communication requirements. The router is a key component of the communication network which is referred as its backbone. Since the router occupies the largest area on the chip and it is the most widely used network component, in this paper, the architecture of the router in the network on the chip is examined and its roles with its components and their effect on the performance of the network are investigated, considering the parameters including time (delay), the area and more importantly the power consumption. It is shown that any modification, combination, or correction in any of the component effect on power consumption of the router and hence on the power consumption of the whole chip. To this end, the related works are examined to make an appropriate estimation of their analogy. This article will help researchers who are trying to design an optimal router based on power consumption.