Majlesi Journal of Multimedia Processing
Volume:4 Issue: 2, Jun 2015

Semantic annotation of images has emerged as an important research topic due to its potential application on both image understanding and database image search or web image search. Image annotation is a technique to choosing appropriate labels for images with extracting effective and hidden feature in pictures. In this paper we proposed method used combination of ImagNet ontology to has hierarchical classification and stochastic indexing that extract effective features by integrates visual topics (global distribution of topics over an image) and regional contexts (relationship between the regions) to automatic image annotation. Regional contexts and visual topics extracted from the image and are incorporated based on TOPSIS (Technique for Order Preference by Similarity to the Ideal Solution) method. Regional contexts and visual topics are learned by PLSA (Probability Latent Semantic Analysis) from the training data. Experiments conducted on the 5k Corel dataset show the proposed method of image annotation in addition to reducing the complexity of the classification increased accuracy compared to the another methods.

The problem of separating speech from background music is a fascinating but difficult and challenging problem for the lack of information about the original music and speech. In this article, we used the discrete wavelet transform for using the time-frequency information of the combined signal. In the proposed method after obtaining the energy of the decomposed wavelet coefficients, these coefficients are classified using SOM neural network. The experimental results, confirmed the capability of the proposed method in mean opinion score (MOS) and signal distortion ratio (SDR) results.

Character recognition is very useful in various fields of engineering applications. Due to visual remarkable ability of humans, this paper describes a simple biological inspired model based on Spiking Neural Network (SNN) for recognizing characters. Two datasets are used: MNIST for recognizing English characters and Bani Nick Pardazesh dataset for recognizing Persian characters. The proposed network is a two layered structure consisting of Integrate and Fire (IF) and active dendrite neurons. In order to train first layer of this network, a proposed algorithm based on k-means is used. Furthermore, a modified algorithm based on Spike Time Dependent Plasticity (STDP) is used in order to train second layer of this network. This structure is designed in way that can be implemented on Field Programming Gate Array (FPGA) properly. Implementation results demonstrate that this model occupies not many resources and also it is very fast in character recognition applications. Finally by applying test data, the proposed neural structure has been evaluated. Simulation results indicate high accuracy of recognizing characters.

While the demand for bandwidth increases exponentially with the growing number of internet based devices, traditional TCP algorithms are turning to be sub optimal. Delay-based congestion control algorithms which are designed to overcome this challenge, are proven to be more satisfactory than loss-based congestion algorithms. On the one hand, Loss base congestion detection technique depends solely on packet loss. On the other hand delay-based algorithms have the advantage of proactively detecting congestion occurrences based on packet delays and as a result avoiding unnecessary packet loss. TCP-Vegas as the most referred variant of delay-based algorithms is promised to achieve between 40 and 70 percent better throughput. However there is some problems which are preventing TCP-Vegas to become widespread. One of these problems is lack of fairness in bandwidth allocation while delay and loss-based connection share a link. In this paper we made some modifications on the original TCP-Vegas which enabled the new algorithm to compete fairly with loss-based algorithm.

A low-power full adder has variuos applications in low complexity and low power multimedia proceeing systems. This paper presents a new structure of 1-bit full adder for sub-threshold technology. It compares full adder sub-circuits and also compares the proposed full adder with common full adders in terms of propagation delay, power consumption, power delay product and square power delay product in sub-threshold voltage technology. HSPICE simulations show that the power dissipation, power delay product and square power delay product of the proposed 17T full adder is 12%, 7% and 17% better than the best common full adder SRCPL, respectively. The full adder circuits are compared in 260 (mV) supply voltage.