Hardware Implementation of LMS-Based Adaptive Noise Cancellation Core with Low Resource Utilization

A hardware implementation of adaptive noise cancellation (ANC) core is proposed. Adaptive filters are widely used in different applications such as adaptive noise cancellation, prediction, equalization, inverse modeling and system identification. FIR adaptive filters are mostly used because of their low computation costs and their linear phase. Least mean squared algorithm (LMS) is used to train FIR adaptive filter weights. Advances in semiconductor technology especially in digital signal processors (DSP) and field programmable gate arrays (FPGA) with hundreds of mega hertz in speed, will allow digital designers to embed essential digital signal processing units in small chips. But designing a synthesizable core on an FPGA is not always as simple as DSP chips due to complexity and limitations of FPGAs. In this paper we design an LMS-based FIR adaptive filter for adaptive noise cancellation based on VHDL97 hardware description language (HDL) and Xilinx SPARTAN3E (XC3S500E) which utilizes low resources and is high performance and FPGA-brand independent so can be implemented on different FPGA brands (Xilinx, ALTERA, ACTEL). Simulations are done in MODELSIM and MATLAB and implementation is done with Xilinx ISE. Finally, result are compared with other papers for better judgment.