Gain Enhancement and Noise Figure Improvement of Low Noise Amplifiers in 0.13 μm CMOS Technology for UWB Applications

A novel CMOS wideband low-noise amplifier (LNA) with a new architecture of high gain, low NF and low power-consumption is proposed. This architecture consists of two non-uniform stages. In order to achieve high power gain (S21) and low power consumption, a current reused with resistive feedback based on an inverter-type amplifier is utilized at the first stage. The second stage of this circuit is used to increase the bandwidth and power gain. Simulation results show that the proposed LNA achieves a power gain between 19±.3 dB. The input return loss (s11) and output return loss (s22) are better than -10 dB. The noise figure (NF) of the proposed LNA is between 2~3.6 dB and reverse gain (S12) is below -30 dB for 3.1~10.6 GHz bandwidth. The input third-order intercept point (IIP3) and power consumption of the proposed LNA are -5 dBm and 13.6 mW, respectively.