Design of an Optimum BCH Decoder to Increase the Reliability of Data Storage and Error Correction Mechanism in Flash Memories

The shrinking of transistor dimensions and migration to nanometer region have increased the data storage errors in new generations of flash memories. Therefore, the reliability of data storage is an important challenge in the structure of these memories. In order to confront with this challenge, BCH error correction codes are utilized in the controller of these memories. There are two important points in the optimization process of a BCH decoder: speeding up the computation and reducing the hardware complexity. To speed up the decoding process, a parallel architecture is utilized for various building blocks. A Pipeline scheme is also adopted in BCH decoder to increase the throughput. To implement this parallel BCH decoder in an area-efficient manner, an iterative matching scheme is proposed to reduce the Chien search hardware complexity by reducing the number of XOR gates through removing the duplicate gates and sharing the remaining ones. The proposed decoder along with BCH encoder have been implemented in VHDL hardware definition language and synthesized in Xilinx ISE. The proposed decoder has been implemented in VHDL hardware definition language and synthesized in Xilinx ISE. The simulation results show that the proposed algorithm could reduce the decoding time and hardware complexity .