design and simulation of clock and data recovery integrated circuitretrieval at 5 Gbps with fast phase locking method for high speed telecommunication recivers

in this paper,the design and simulation of an integrated circuit for clock and data recovery at a data rate of 5 Gbps has been dealt with in the middle phase method . clock and dat recovery circuits are of particular importance in optical communication and play a key role in high speed receivers . the proposed circuit is designed and simulated using an intermediate phase method and using CMOS technology of 0.18 micrometers in the ADS simulator.the result indicate that the circuit with the PRBS input data can recover the data in a very small time .the amount of jitter in the recoverd data is 16 pico second.