Improved Low Voltage Low Power Recycling Folded Fully Differential Cascode Amplifier

In this paper, a novel structure for folded cascode low-voltage low-power fully differential amplifier is proposed. Both conventional folded cascode amplifier and recycling folded Cascode amplifier is simulated which in later case the DC gain, gain bandwidth and input referred noise is improved thank to the higher transconductance of recycling structure. Meanwhile the phase margin is reduced in recycling folded cascode amplifier which is compensated by improved recycling folded cascode amplifier circuit proposed. Amplifiers are simulated by Cadence software utilizing 180 nm TSMC technology. DC gain, bandwidth and phase margin of conventional folded cascode (FC), recycling folded cascode (RFC) and improved recycling folded cascode (IRFC) are obtained 42.09dB, 23.24kHz, 90.14°, 48.27dB, 83.16kHz, 82.51° and 58.92dB, 66.58kHz, 84.12°, respectively. Post layout simulation for improved recycling folded cascode (IRFC) is provided which proves the proper functionality of the proposed structure. For fair evaluation all structures are simulated in identical circumstance and transistor aspect ratios. The power consumption of these circuits are obtained 700 nW, 700 nW, 750 nW, respectively. High figure of merit (FOM) for proposed amplifier in comparison with its other counterparts represents its improved performance.