Design of Floating-Point Multipliers with Normal and Fault-Tolerant Operations Using Reduced-Precision Computin

Multiplication is one of the important computations required for different signal processing applications especially regarding voice and image. However, the multipliers as digital circuits are susceptible to different environmental effects such as noises. In this paper, a new approach is proposed for designing a 32-bit floating-point multiplier which can operate in two operational modes, normal and fault-tolerant, dependent to the environmental conditions. In the fault-tolerant mode, by reducing the normal precision and accepting a negligible error in the output, a portion of preliminary circuit is released which is used for redundant computations in order to detect or correct errors. This way, two multiplier architectures with error detection or correction capability are proposed that have a beneficial reliability against different types of permanent and transient faults. The implementation results show that in the fault-tolerant mode, maintaining 13 bits instead of 23 bits for the mantissa will be enough to achieve an error detecting multiplier, and maintaining 11 bits will be enough to achieve an error correcting multiplier with acceptable area and power overheads (from 12% to 26%) while their precisions are enough for most applications.