Analysis and Evaluation of the Effect of Design Parameters on Timing Parameters and Power Consumption of Static Flip-Flop in 16 nm Technology Node

Flip-flop is one of the important elements in the digital circuit’s design, which its performance affects the speed and power of the system. In this paper, appropriate simulations are used to obtain the timing parameters of the static flip-flop and investigate the effect of the width of different transistors on these parameters. Then, the effects of the supply voltage and manufacturing process parameters variation on the performance of the flip-flop are investigated. The widths of transistors are determined based on the desired energy-delay product (EDP) and power-delay product (PDP) for these two cases separately. Then, the effect of voltage variations on the increase of EDP and PDP are investigated compared to the base flip-flop. We used a static D-type flip-flop in our simulations. The simulations were performed using the HSPICE in 16 nm technology node at 1 GHz frequency.