A Survey on Settling Behavior of Control Voltage in Phase Locked Loop Circuits Considering Non-Ideal Effects and Sensitivity to Circuit Components Variations

This paper comprehensively investigates how the control voltage settles in Voltage Controlled Oscillators (VCO) by considering all non-ideal factors in phase lock loop circuits. Also, the different structures of the phase detector and their effect on the locking speed of the phase-locking loop circuit, the control voltage ripple and the locking frequency range will be compared. Three phase locked loop circuits with XOR detector, RS-FF detector and dynamic phase detector were investigated in this paper. The simulations were performed on 0.18 µm-CMOS technology with a 1.8V power supply. The simulation results show that the operating range of the phase-locked loop circuit including dynamic phase detector with charge pump circuit has less ripple for the non-ideal effects compared to the phase-locked loop circuit including XOR phase detector and the phase-locked loop circuit including RS-FF phase detector. of the phase-locked loop circuit including dynamic phase detector is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, frequency range is 0.284-3.33GHz, power consumption is 2.86mW and phase noise is -118.8dBc/Hz.