An Overview of Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGA). In order for these systems to be fielded in harsh environments where high availability and reliability are a requirement, the programs running on FPGAs must be hardware fault tolerant, as this is the case during the lifetime of the system. may occur In this paper, we present new fault tolerance techniques for FPGA logic blocks, which are developed as part of the Self-Standing Test Areas (STAR) approach for test and diagnosis, and online configuration (we tolerate over 100 logic faults through the actual implementation on an FPGA containing a 20 x 20 array of logic blocks). A key feature is the reuse of incomplete logic blocks to increase the number of effective spares and extend mission length. To increase fault tolerance, we not only use faulty non-faulty sections or logic blocks with minor faults, but also use faulted sections of faulty logic blocks in non-faulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of available spare logic resources. Unlike many row, column, and piecewise methods, our multi-level approach can tolerate faults that are evenly distributed over the logic area, while also clustering faults in the same local area. Meanwhile, system operations are not interrupted for fault detection or computational fault-transitor configurations. Our fault tolerance techniques are implemented using ORAC2 series FPGAs that specify incremental dynamic runtime configuration