A Multiplier-Less Discrete Cosine Transform Architecture Using a Majority Logic-Based Approximate Full Adder

This paper proposes a new approximate full adder (FA) based on the majority logic (ML) concept. The fundamental structure of the ML concept is a 3-input majority voter and is widely utilized in digital arithmetic cells. The ML-based proposed FA works at low power, small delay, and low power-delay-product (PDP). The carbon nanotube field-effect transistor (CNTFET) technology lowers the FA power, while the gate diffusion input (GDI) technique is used as the main technique. The swing issue of the GDI technique is resolved by the dynamic threshold (DT) technique. Compared with its exact circuit, the proposed FA saves 2 majority gates, 3 inverters, and a 4.02 ns delay. In the proposed FA, the PDP is improved by 53.73%. The product of the PDP and the normalized mean error distance (NMED) is called PDPE, and in the presented FA, it is reduced by 9.50%. Moreover, the proposed FA is embedded into a multiplier-less discrete cosine transform (DCT) design, which is an appropriate circuit for very large-scale integration (VLSI) systems. The 8-input DCT architecture consumed 2.2321 mW of power for each DCT operation. Also, the circuit has better performance in terms of PDP-area-product (PDAP). The results of DCT implementations confirm the efficiency of the FA.