Design of Low Power High Speed Dilation Operator for Binary Images in CMOS Technology

This paper describes the design of hybrid wave-pipeline architecture for implementation of real time morphological dilation. With minor changes to this architecture, it can be utilized for erosion, closing, and opening operators. The new architecture results in higher speed, less hardware complexity, and lower area and power dissipation compared to conventional pipeline implementation. In addition, it is faster than the wave-pipeline structure, without the difficulty of balancing the delay of long signal paths. Using the new architecture, three ASIC chips in 0.18µm CMOS are designed for binary image processing through Verilog. These chips dilate a 1024×1024 image by a 21×21 structuring element in 256.58μ s. The maximum frequency of the operations is 5.882 GHz, 5 GHz, and 4.167 GHz. For the power supply of 1.8 V and the 4.167 GHz frequency, the power dissipation is 597mW, 478 mW, and 410 mW, and the chip area is 0.118 mm2, 0.087 mm2, and 0.075 mm2, respectively.