Design and Implementation of AES Encryption Engine on FPGA for High-speed Links

Advanced Encryption Standard (AES) is one of the most common standard encryption algorithms. Inspired by its characteristics, AES algorithm can be implemented on various hardware platforms such as FPGA. Also, the data path can be implemented in either loop-unrolling or rolling architecture. These two architectures have direct impact on the amount of area consumption on the chip as well as system throughput. Then, a smart design should be able to consider the trade-off between area and throughput and provide a good balance between these two conflicting factors. In this paper, we propose such a design to represent the area-throughput trade-off for FPGA implementation of the AES algorithm. With loop unrolling and pipelining techniques, throughput of 71.35 Gbps is achievable in Virtex 7 FPGA (xc7v585t-3ff1157). This design has just used 3669 Slices on the chip. The extracted results from the Place & Route report of Xilinx ISE 14.2 indicates that the maximum attainable clock frequency is 570.776 MHz.