A Low-Power CMOS Optical Communication Front-End Using a Three-Stage TIA for 5Gb/s Applications

In this paper, an optical communication receiver system for 5Gbps applications is proposed concerning power consumption. An inductor-less circuit in three-stages is proposed as the trans-impedance amplifier (TIA), which benefits from the inherent low input resistance of a common gate topology as the first stage. By forming two zeros in this TIA, proper frequency response is obtained while the DC current is reduced. In order to obtain extra gain for the receiver system, three stages of a conventional limiting amplifier (LA) are used. In order to verify the circuit performance, the proposed receiver is simulated in HSPICE using 90nm CMOS technology parameters. The receiver is mathematically studied and is matched with the simulations. Simulations, such as eye-diagram, noise analysis and fabrication process analysis (Monte-Carlo) are done in this paper. The proposed TIA shows 53.9dbΩ trans-impedance gain, 3.5GHz bandwidth, 15.2pA/√Hz and only 1.52mw power consumption for 1.2v supply voltage, and the receiver system shows 90.9dbΩ, 3.5GHz bandwidth and 6.34mw power consumption (for 2stages of TIA and 3stages of LA) for 1.2v supply voltage. Results indicate that the proposed receiver is suitable to work as a low-power 5Gbps optical communication receiver system.