Improvement of PFD Based on Pulse Latched For Increasing Phase Detection Range and Operating Frequency

In this paper, an improved phase frequency detector circuit based on pulse latched is presented. The proposed PFD include a pulse generator, a simple latch circuit, and a reset circuit. By reducing the reset time the blind zone is decreased. This idea leads to an increasing phase detection range more than 16 degrees and an operating frequency more than 500 MHz. Also in this design input signals are used instead of the output signals to reset the PFD. The significant advantage of this design compare to the prior PFD is obtained detection range increased 330 degree to 348 degree at 435 MHz. In addition the time of reset improving, the pulse generator circuit has lifted which led to increasing the speed of designed PFD. The designed PFD are implemented in CMOS 0.18μm TSMC technology and its area is 24 μm × 23 μm .The post lay out simulation results indicate that it has a good performance up to the frequency of 2 GHz. The power dissipation is 201 μW from a 1.8V power supply at 435 MHz.