Continuous Time Feedforward Quadrature Delta Sigma Modulator Design Omitting the Power Hungry adders for LOW-IF Receivers

This article proposes a new method to design a third order low pass CTFFQDSM sharing the last integrators instead of adders. The removal of adders is done using a new technique in such a way that neither any extra block is added nor any modulator loop function is changed. Therefore, power consumption and chip area can be reduced. This 3-bit modulator centering at 1MHz with 2MHz band width is designed for WCDMA standard and is implemented in 180nmCMOS. Signal-to-noise ratio of 75.9 dB for over sampling ratio of 32 is obtained. Figure of Merit obtained from the proposed modulator is improved by more than 10% compared to the previous design methods and reaches about 0.339 (pj / conv).