Modeling and Calibration of Linear and Nonlinear Gain Factors in Different Stages of Pipelined Analog-to-Digital Converters Using a Modified Correlation Algorithm

Most of the integrated components used in current CMOS integrated circuits (IC) technology are inevitably nonlinear. This issue complicates the matching between such elements, and affects strongly the performance of analog circuits. In data converters, the nonlinearity caused by employing nonlinear transistors lowers the overall resolution and may limit the number of bits to an unacceptable value. It can be demonstrated that the number of the stages that should be calibrated is equal to the difference between the maximum number of bits without calibration and the desired number of bits which should be calibrated. In this article, we modeled the main error sources of the gain factor in pipeline stages. A modified calibration technique is then applied to estimate and to calibrate the nonlinear gain factor of the primitive stages. The effectiveness of the proposed approach is verified through design and calibration of a 14-bit 65MS/s converter in 0.18µm standard CMOS technology.