A 2-bit Full Comparator Design with Minimum Quantum Cost Function in Quantum-Dot Cellular Automata

In recent years, reduction of the complementary metal-oxide-semiconductor (CMOS) circuit feature size has caused significant challenges, such as current loss and leakage, and high power consumption. Therefore, further reduction of the size of CMOS technology is not feasible. Quantum-dot cellular automata (QCA) is an emerging technology at the nanoscale, which can utilize for designing computers and very-large-scale integration (VLSI) circuits in the near future. QCA technology makes it possible to design low-power, high-performance, and area-efficient logical circuits. A comparator function is a digital logical function, which compares whether a bit is greater than, smaller than or equal to the other bit or not (half comparator). Full comparator has a third input, which shows the result of the previous step. Half and full comparators play an essential role in CPU architecture. In this paper, a full comparator circuit based on the QCA and a new quantum cost function is proposed. Besides a 2-bit comparator is presented based on the introduced full comparator. Using the new quantum cost function the proposed full comparator design is compared with the previously presented designs in terms of area, delay, and complexity. Comparisons show that the proposed design has less area and delay and therefore, it is more suitable for utilizing in CPU design.