Improvement in the Performance of Tunneling Carbon Nanotube Field Effects Transistor in Presence of Underlap

Underlap between gate and drain/source area is one of the important items non-ideal effects in the device manufacturing process in the nanometer scale. In this paper, for the first time, the effect of underlap between the gate and drain/source area for tunneling carbon nanotube field effects transistor is investigated. To simulate the device, self- consistent solution of Schrodinger and Poisson equations and Non-equilibrium Green’s Function method have been employed. The function of the device is evaluated in terms of the on-state current, off-state current, current ratio, sub-threshold swing, delay time, and the power delay product. The simulation results show that the underlap effect improves some of the device characteristics and has some adverse effects on other characteristics. In the case where the length of underlap area is optimally chosen, the device performance will be improved considerably. Simulation results indicate that underlap significantly reduces the off-state current and thus reduces band-to-band tunneling and ambipolar behavior of the device. Also, the underlap effect by improving the power delay product parameter is a suitable option for low power applications compared with the conventional structure.