BIMS: Built-in Intermediate Memory Structure to Improve Multi-Level Phase Change Memories

In this paper, we propose a Built-in Intermediate Memory Structure (BIMS) to improve the efficiency of main memory architectures based on Phase Change Memory (PCM). It exploits the capability of the PCM device which can be used as both multilevel cell (MLC) and single-level cell (SLC) during the processor operation. The proposed structure invokes physical pages with MLC devices for a normal data storage. By utilizing an internal page management mechanism, however, it turns memory cells of some unused physical pages into the SLC mode. BIMS exploits such pages to provide an intermediate layer for the memory read and write requests with better access time and lower energy consumption. This intermediate layer diminishes most of the accesses to the pages with the MLC devices by absorbing most of the incoming memory requests.