Design of Serial to Parallel Converter with High Speed and Low Power for Analog 8-FFT Processor to Jamming Mitigation in GPS Receiver

In this paper, a serial to parallel block for a 8-FFT processor in 0.13 um CMOS technology is presented. Because of more advantages of current mode circuits compared to voltage mode counterparts, in this design, it has been made effort to utilize these merits. Then, at first input voltage signal should be converted to current signal to be processed in current mode. After that, to parallel current signal the current mode sample and hold is employed. Two banks sample and hold are placed in proposed block diagram to synchronize 8 samples at the FFT input. The suggested serial to parallel block has the capability of producing the required samples at the same time with lower power consumption and higher speed. Also, because of applying the class AB current mirror the sample and hold is able to convey both peaks of the signal. It is shown that the power consumption of voltage to current converter is about 3 mW and each sample and hold draws 100 uA of 1.2 V power supply. Moreover, the whole block has approximately 5 mW power consumption. The 3dB frequency is placed at 125 MHz which impose limitation on sampling frequency of sample and hold circuit. In our application that is jamming mitigation in Global Positioning System (GPS) this limitation can be ignored because of low intermediate frequency (4MHz) of GPS.