A High Resolution, Time-to-Digital Converter Design Based on Parallel Vernier Ring

In this paper a time-to-digital converter, based on parallel vernier ring oscillator is presented. The delay elements have been applied in parallel form to two ring oscillators with different frequencies. The delay difference of the time-to-digital converter stages’ can be less than an inverter delay’ because of using parallel elements. simultaneous use of parallel delay elements and vernier method, The proposed time-to-digital converter can be achieved high resolution. The signal gating method is used to reduce power consumption. In this method, when the lag signal reaches the lead one, by determining the digital output code, the control signal is activated and stops the fluctuations in two ring oscillators, thus it prevents power dissipation. A typical 6 bit time-to-digital converter with the proposed method is simulated in 65nm standard CMOS technology. 1ps resolution, 382uW average power consumption, 2269um2 chip area and 600Ms/s sampling rate is obtained under 1V power supply.