High PerformanceLow Latency16×16 bit Booth Multiplier usingNovel 4-2 Compressor Structure

In this article, the design procedure of a low latency Booth multiplier has been proposed. With the help of a novel 4-2 compressor, a high-performance16×16bitBoothmultiplier has been implemented,which depicts high operating frequency. To achieve this, the proposed 4-2 compressor has been utilized successively in the Partial Product Reduction Tree (PPRT) of the multiplier and by means of radix-4 Booth scheme,the multiplierhas been designed.The Partial Product (PP) generation circuitry is also based on the other work published by the authors which enables the designed structureto workat the frequency of 350MHz. The main advantage of the designed compressor is the elimination of the middle stage inverters between cascaded blocks of PPRT which considerably enhances the speed of whole system. Simulation results for TSMC 0.18μm CMOS technology and 1.8V power supply have been demonstrated to confirm thecorrect operationof proposed4-2 compressor.According to the results, the achieveddelay ofthe critical pathfor hard testand high capacitive load,equal to100fF,is936pswhileapower consumption of 255.15μWhas been achieved at the operating frequency of 100MHZ.