A New Highly Accurate Translinear Based CMOS Multiplier in Current Mode with Low Power Dissipation

This paper deals with a new strategy for design of analog multiplier which operates in four quadrant. The proposed circuit employs the dual translinear principle with composition of NMOS and PMOS transistors, simultaneously. The important achievements of the circuit are its wide bandwidth, low power consumption as well as the body effect free performance. In order to demonstrate efficiency of the circuit, harmonic distortion analysis due to the mismatch in input signals (IX , IY), transconductance parameters (K) and threshold voltage (Vth) are discussed in detail, and the obtained relations verify the simulation results and indicate the robustness of the circuit in the presence of mismatch. Also, to validate the circuit performance, it is used in two useful applications of amplitude modulator and frequency doubler, and the simulation results of them are presented. Additionally, the Monte Carlo analysis for transistor parameters as well as the temperature variation results demonstrate stable performance of the circuit. This circuit is designed and simulated using HSPICE software with TSMC and level 49 parameters (BSIM3v3) in 180nm technology. The simulation results demonstrate a linearity error of 0.69%, a THD of 1.05% in 1MHz, a -3dB bandwidth of 1.17GHz and a maximum power consumption of 93µW.