Design of a fast fault detection circuit in underwater network communications

Because of existing noise in the underwater communications, data are susceptible to error and sending such packets will reduce network lifetime. Applying redundant coding for error detection is necessary in noisy enviroments, to solve this challenge. Also, due to the low processing power and limited energy of the nodes, using fast coding with low power consumption is common. The residue number system is an example of these condings. In this paper, a reverse converter is designed for moduli set {2^n-1, 2^n+1, 2^2n} in this system for error detection. Forms of modulus cause to have a larger dynamic range and using Chinese remainder theorem, leads to have a high-speed with low-area consumption circuit. Both unit gate model and VHDL simulation in ISE 13.1 based on delay and area comsumption are used to compare the proposed circuit and previously presented approaches. The results indicate a significant improvement in the area and time complexity of the proposed circuit in large dynamic ranges, as a result the life of the network will increases.