Asymmetric Gate Oxide Thickness Technology for Reduction of Gate Induced Drain Leakage Current in Nanoscale Single Gate SOI MOSFET

Gate Induced Drain Leakage (GIDL) current is one of the main leakage current components in Silicon on Insulator (SOI) MOSFET structure and plays an important role in the data retention time of DRAM cells. GIDL can dominate the drain leakage current at zero bias and will limit the scalability of the structure for low power applications. In this paper we propose a novel technique for reducing GIDL and hence off-state current in the nanoscale single gate SOI MOSFET structure. The proposed structure employs asymmetric gate oxide thickness which can reduce GIDL current and hence Ioff current to about 98% in comparison with the symmetric gate oxide thickness structure, without sacrificing the driving current and losing gate control over the channel. This technique is very simple in the fabrication point of view in CMOS technology.