نشریه مهندسی برق و مهندسی کامپیوتر ایران
سال پانزدهم شماره 1 (پیاپی 42، بهار 1396)

In this paper, a new criterion is introduced for solving optimization problems on stochastic graphs- as a model of computer networks-by stochastic learning Automata. This proposed method, because of considering estimated variance of response of environment, can better adaptation to changes of environment. As a result, the proposed method can produce better response to learning Automata actions.
The proposed method, by entering a noise, can avoid learning Automata being stuck at a local optimum point. Our simulation shows that this proposed method can be improve the convergence rate of Automata-based algorithm.

A major challenge in the field of platforms and applications is how to display and combine the results of real-time and static partitions, as well as reduce the response time of on-line analytical processing queries in a near real-time data warehouse. So appropriate content in a near real-time data warehouse can be produced through a common interface for the results of queries. This article provides an architecture that includes an XML/XSLT interface approach to generate appropriate content and also creating materialized views in the client side. In this architecture, providing a model-based HTML output, distribution and composition of results, are presented. In addition, two parallel approaches for incorporating the results of real-time and static partitions of near real-time data warehouse architecture are proposed. In the proposed architecture, the fundamental role of XML and its related technologies, the production and maintenance of content in near real-time data warehouse is determined. The results show that response time of on-line analytical processing queries via materialized views in the server and client side is reduced. Introduced functions for selecting materialized views in the both of client and server sides improve the storage space.

In this paper, the binary quantum-inspired gravitational search algorithm is adapted to dynamically optimize the design of a wireless sensor network towards improving energy consumption and extending the lifetime of the network, so that the application-specific requirements and communication constraints are fulfilled. The proposed approach is applied on a wireless sensor network used in the application of precise agriculture to monitor environmental conditions. This algorithm would present an optimal design detecting operational mode of each sensor including cluster head, high signal range, low signal range and inactive modes taking into consideration the constraints of the network. The simulation results indicate the most performance of the proposed method in comparison with binary genetic algorithm and particle swarm optimization.

In this paper a fast, reliable and robust algorithm against occlusion for visual tracking of a pre-defined target in sequence images based on adapting template of target edges with search space edges is presented. At first, target window is specified by user and then the proposed algorithm determines an appropriate model for the target by choosing the best edges of the target window. Moreover, to increase robustness against occlusion, target model has been divided into four equal divisions and by performing a logical AND between the template of each division edges and search space edges and then by counting its non-zero pixels, resemblance matrix for each division of target is obtained. In a case that values of the resemblance matrix are less than values of threshold matrix, the desired division is considered occluded and then by taking the effects of non-occluded divisions into account, the exact location of the target in each frame is determined. In the tracking values, in case of appropriate condition respect to background condition, the model of target edges is updated. Selecting dominant edges, multi dividing and updating the target template, has resulted in increasing the robustness of the algorithm against some vital challenges such as changing in ambient and target light, and occurring occlusion over target. The simplicity of this algorithm has provided the possibility of real-time implementation in OpenCV environment using C language, that achieves averagely to more than 60 frames per second for a computer with 2.6 GHZ CPU and 4 GB RAM. Moreover, comparing the results of the proposed algorithm to other algorithms, revealed a higher speed and greater reliability.

One of the most fitting biometric for identifying individuals is finger veins. In this paper, we study the human recognition via finger vein images that recognize persons at a high level of accuracy. First we use entropy based thresholding for segmentation and extraction veins from finger vein images. The method extract veins as well, but the images are very noisy. That means in addition to the veins that appeared as dark lines, they have some Intersecting lines. Then we applied radon transformation to segmented images. The radon transform is not sensitive to the noise in the images due to its integral nature, so in comparison with other methods is more resistant to noise. This transform does not require the extraction of vein lines accurately, that can help to increase accuracy and speed. Then for extracting features from finger vein images, common spatial patterns are appliedto the blocks of Radon Transform. In identification step two methods are used: Nearest Neighbor (1-NN) and Artificial Neural Network (MLP). Experiments conducted on sets of finger vein image database of Peking University show 99.6753 percent success rate in identifying individuals.

We may investigate the correctness of dynamic fuzzy models by a combination of Modal Temporal Logics and Fuzzy Logic. So far Fuzzy-extended Kripke structure (FzKripke) and Fuzzy-extended Program Graph (FzPG) are introduced as two timed Fuzzy logic models. Meanwhile, a Fuzzy-extended Temporal Logic (FzCTL) is introduced. Although no verification technique is devised for verifying FzCTL properties of timed Fuzzy logic models, its applications in verification of Fuzzy Logic Circuits (i.e., Fuzzy Flip-Flops) are studied and elaborated. In this paper we introduce a symbolic approach to tackle the state space explosion problem in timed Fuzzy logic models with which models are simultaneously compressed and processed in the most compact representation possible yet. The applicability of this approach is also demonstrated through experiments on a case study concerning dynamic hazards in a Fuzzy D-Flip Flop. Performance measures like runtime and memory consumptions are also provided for different scenarios.

We may investigate the correctness of dynamic fuzzy models by a combination of Modal Temporal Logics and Fuzzy Logic. So far Fuzzy-extended Kripke structure (FzKripke) and Fuzzy-extended Program Graph (FzPG) are introduced as two timed Fuzzy logic models. Meanwhile, a Fuzzy-extended Temporal Logic (FzCTL) is introduced. Although no verification technique is devised for verifying FzCTL properties of timed Fuzzy logic models, its applications in verification of Fuzzy Logic Circuits (i.e., Fuzzy Flip-Flops) are studied and elaborated. In this paper we introduce a symbolic approach to tackle the state space explosion problem in timed Fuzzy logic models with which models are simultaneously compressed and processed in the most compact representation possible yet. The applicability of this approach is also demonstrated through experiments on a case study concerning dynamic hazards in a Fuzzy D-Flip Flop. Performance measures like runtime and memory consumptions are also provided for different scenarios.

Recently, decimal arithmetic has received renewed attention in certain application domains such as financial computations. This is mostly due to the demand for more accurate decimal number representation and calculation in those applications. While decimal arithmetic may be implemented in software and hardware, the latter form offers higher speeds and better performance. Traditionally, hardware decimal units have been designed as application-specific specialized hardware modules. However, emerging designs have come with some degree of reconfigurablility. But there is no research on the effects of reconfigurability parameters, such as granularity and degree of flexibility, on the overall characteristics of decimal hardware modules .In this paper, it will be shown that bit-level granularity is not suitable for decimal reconfigurable adders. Instead, digit-level granularity will lead to superior designs. The synthesis results indicate that increasing granularity level provides an area improvement of %12 and power improvement of %13.4. Unlike adders, increasing the granularity of decimal multipliers has an adverse effect on their quality and may cause up to %75 increase in their area and power consumption.