نشریه صنایع الکترونیک
سال هشتم شماره 2 (پیاپی 29، تابستان 1396)

Fuzzy cognitive maps (FCMs) that are soft computing techniques, by combining fuzzy logic and neural network theory, have been known as a powerful tool for modeling complex systems. Utilization of different learning algorithms to overcome the weaknesses of this model, is one of the active area of science. In this paper, a new hybrid algorithm based on nonlinear Hebbian learning and real-coded genetic algorithm is introduced, which operate in an entangled way and by improving the characteristics of each of these two algorithms, can be applied in different decision-making models with high precision. The proposed model is implemented on a process control problem.

This work presents a Dual-mode VCO with noise filtering. By using dual-mode resonators, an oscillator is designed for two different frequency bands. Also, a properly designed noise filter in the tail current source reduces phase noise of LC-VCO. The dual-mode resonator circuit can be changed by adjusting the frequency range with capacitor bank and varactor in both frequency mode. Also, phase noise is improved in both frequency mode by current source filter. The VCO has been simulated in a standard 0. 18µm CMOS process; it covers tuning range between 6. 27 GHz - 8. 08 GHz and 10. 65 GHz - 13. 02 GHz. The simulated VCO achieves a phase noise of -120‎ dBc/Hz from the 6. 83GHz carrier, and -113. 8 dBc/Hz from the 10. 61 GHz carrier at 1-MHz offset, while the power consumption is 14. 15 mW from a 1. 5V supply. The calculated figure of merit of this VCO is between -170 dBc/Hz and -184. 31 dBc/Hz.

The growth of internet services and business dependency on them makes it necessary to assess services weakness before operating them. In its network branch, this needs modelling internet traffic similar to the real world traffic. Single platforms which support generating heavy traffic are costly. Therefore, we introduce a toolkit named Distributed Variant Traffic Generator (DVTG) which has two main advantages. It is able to generate heavy traffic via a cluster of simple machines and is capable of making diversity in the generating traffic by implementing and embedding various protocols. The tool uses statistical techniques to simulate the actual behavior of network traffic. DVTG can be used to evaluated performance of network and its elements such as switch, router and firewall. Experiments illustrate more than nine gigabits throughput using ten machines each has one gigabits network card. So, the overhead is less than 10 percent.

This paper studies the problem of binary RS code parameters estimation in noisy scenario. This problem comes to military applications as well as cognitive radio receivers design. Despite the widespread application of the RS codes, so far just a few methods have been proposed to solve it. Most of these have a high complexity and are effective only in the very low noise. This paper proposes a new, effective and low-complexity method to identify the RS code parameters. In this method, the code length and primitive polynomial and then message length is determined. The estimation of parameters is based on the identification of a special set. The main feature of this set is the presence of transmitted codewords in the all codes belonging to it. In this paper, a test is proposed to identify the set codes. In this test, the parity check bits are generated again by the received message bits, and then compared with the received parity check bits. If the number of bit differences is greater than the threshold, presence of RS code is verified in the set. In this paper, two appropriate thresholds are proposed. The first threshold is designed based on Minimax decision rule and is depended on the channel error. However, the second threshold is experimental and is independent of channel error. The simulation verifies the high performance of this method. For example, the method can perfectly estimate the parameters of RS code with length of 63 up to 4×10-3 error rate.

In this paper, a re-synthesize technique based on the local logical replacement in order to reduce the soft error rate of combinational circuits is proposed. The proposed method provides an innovative technique to increase the logical masking probability considering the area overhead. In this technique, at first, using an extended Quine-McCluskey (QM) method, the sub-circuits be extracted from the main circuit; while, different implementation carried out on the extracted sub-circuits. In order to choose the best alternative among the different implementations of a sub-circuit with the lowest soft error rate, a new parameter named as Global Failure Probability (GFP) is introduced. Experimental results on some ISCAS’85 benchmarks show that, on average, a probability of circuit failure reduction of 17. 75% is achieved compared to the original circuit. The average area overhead is 5. 39% of the original circuit.

Question answering system is an important major in natural language processing and information retrieval which has interested a group of researchers in these decades. Question answering systems aim to develop techniques that can go beyond the current information retrieval systems in order to return exact answers to natural language questions. In this research, Persian question answering architecture on non-factoid questions will be proposed. The proposed architecture consists of three components: question processing, document retrieval, and re-ranking. In question processing component required preprocessing was performed and question topic was recognized. In document retrieval component, open source search engine was utilized and machine learning methods were applied for re-ranking task. Our experimental result represents that proposed system has achieved 81. 29 % accuracy and 71. 88 % mean reciprocal rank. It can be stated that our proposed system is the first question answering system with such features in Persian, especially in the religious domain.

The most important challenges in ultra wideband Low Noise Amplifiers (LNAs) are flatness of gain, input impedance matching and lower noise figure at desired frequencies. In this paper, an ultra wideband low noise amplifier with flat gain and low noise figure at frequencies between 3. 1GHz to 10. 6 GHz is proposed. In the proposed circuit, a cascade stage is used as a main block and noise cancellation method is used for increasing gain and lowering noise figure. To have good input and output matching, active feedback is used. In addition feedback and RLC load is used for better flatness for gain of LNA. The proposed circuit is designed and simulated in TSMC 90nm CMOS Technology using HSpice simulator. Simulations show noise figure of 1. 62-2. 1dB, flat gain in the range of 11. 9-12dB and power consumption of 11. 72mW in the frequency range of 3. 1-10. 6GHz.

This article is about of aperture size and opening angle of horn flare of wideband antennas effects, on the amplitude and phase patterns. In this study, behavior of amplitude pattern of wideband horn antenna in the E-plane and H-plane and effect of magnetic currents and phase distribution of these currents on aperture of two sample antennas are observed.
As we mentioned in above, in this paper two different horn antennas with different physical size were studied.
It is noticeable, that in design of wideband horn antennas, such as (9:1), studies are focused on impedance characteristic and VSWR behavior of antenna. But in this paper for two design of antennas,
By using analytical relations, radiation characteristics of antennas at 4 different frequencies for E-plane and H-plane are calculated. For validation of calculation, two antennas with similar size, in CST studio microwave and HFSS simulators have been simulated.
Results of these studies, show that by increasing frequency, variation of 3-dB beamwidth for E-plane is more than 3-dB beamwidth of H-plane. But variation phase Pattern in E-plane is less than variation of phase pattern of H-plane.

In this paper, the performance of the graphene based terahertz lasers has been studied at room temperature. The study shows that the performance of the laser decreases as the temperature increases and the laser does not even work in some ratios as intensity of incident optical radiation to threshold intensity of optical radiation. Furthermore, to achieve a narrow band laser, laser containing active regions of graphene ribbons has been studied and it is shown that a proper functioning of a narrow band laser is possible for armchair structures at room temperature when the number of atoms that are on either side of the ribbon with widths multiple of three, due to on.

Using metamaterials in antenna design leads to interesting features includes size reduction. Although, the antenna miniaturization is the most promising advantage especially in commercial applications, their narrow band behavior causes great concern for the future progress. In this article, a near-field resonant parasitic (NFRP) antenna addressed. In order to increase the accuracy of antenna model in numerical simulations, a two-port model of the antenna suggested. Based on proposed model an accurate NIC loaded Non-Foster matching designed, simulated and fabricated. Measurement shows fractional bandwidth of about 4. 75% from 268MHz to 280MHz. Due to the sensitivity of NIC circuits to their elements; a detailed parameter study also reported. This investigation clearly shows the antenna impedance response concerning whit the NIC circuit elements.

The goal of this research is designing an analog current-mode time-delay cell based on a current-mode first-order all-pass filter with high output impedance. The proposed all-pass filter as a time-delay cell consists of a class AB cascode current mirror and also a differential input voltage current conveyor (DVCC) as an active element employing only two grounded passive components for phase shifting and required time delay. The proposed time-delay cell is capable of working at low-voltage headroom and has high speed operation and a low-power consumption of 1. 39mW. The value of delay can be controlled by both fine-tuning and coarse-tuning. This time-delay cell can generate a delay of 14ns while it is able to reach a minimum delay of 6ns across a 100MHz bandwidth by using fine-tuning and coarse-tuning of the time-delay cell, as well. The proposed cell can be used in the beamforming, radars, and medical engineering. HSPICE simulations are performed based on a 0. 18µm standard CMOS technology.

Envelope tracking is one the effective techniques of increasing the power efficiency of RF power amplifiers. In this method, a supply modulator is adopted to change the supply voltage of power amplifier proportional to the envelope of the RF signal input to the RF power amplifier. Power efficiency of this modulator greatly affects the total power efficiency. The supply modulator is composed of a linear amplifier and a DC-to-DC convertor. In this paper we present a new structure to increase the power efficiency of a supply modulator. In the proposed structure, a multi level supply is used in the linear amplifier. Our analysis and simulations results show that this technique leads to 11% improvement of the supply modulator power efficiency.

In this paper, a 8T SRAM cell in sub-threshold region is presented which in addition to read and write operation improvements, reduces power consumption significantly. The proposed cell carries out write operation differentially and has a single ended read operation. In this design, using an appropriate combination of techniques, leads to improvements the cell performance. These methods include weakening feedback in the write mode, applying the boosted word line, eliminating one of the driver transistors and isolating storage node from access transistor by a buffer. The simulation results at 32 nm PTM technology and VDD 0. 3 V show the proposed cell improves read and write power consumption 93%and 80%, respectively compared with 6T cell. Moreover, the proposed cell has lower power consumption and stronger write mode compared with other bit interleaving cells. Furthermore, the proposed cell has a desired performance in the read mode.

This paper presents the application of automatic under voltage load tripping and switching of shunt reactors as counter measures for fault induced delayed voltage recovery (FIDVR). As dynamic behavior of loads has significant impact on simulating FIDVR, proper load modeling is also discussed in this paper. Simulations conducted on actual network show that the proposed load model is effectively able to simulate FIDVR. It also shown that automatic under voltage load shedding and switching of shunt reactors can be used as counter measures for reducing risk of voltage collapse or over voltage conditions that may take place following load tripping caused by FIDVR.