فهرست مطالب

  • Volume:7 Issue: 3, 2018
  • تاریخ انتشار: 1397/08/01
  • تعداد عناوین: 6
|
  • Mansoureh Labafniya, Mohammadreza Reshadinejhad , Shahram Etemadi Broujeni Page 89
    adder block is one of the major block in circuit design. inserting efficient adder block will cause having more efficient final design. In this paper improved GDI based adder will be designed. Proposed GDI based adder is more efficient compared to [2] and [4] in delay, performance and PDP. at last an adder/subtractor circuit will be designed.
  • Soorena Zohoori, Mehdi Dolatshahi Page 95
    In this paper, a two-stage 5Gbps transimpedance amplifier (TIA) for an optical communication receiver system is presented. The presented TIA uses a regulated cascode configuration (RGC) as the input stage, which benefits from low input resistance, and is followed by a gain stage with negative feed-back network and a buffer stage in order to provide extra gain to operate properly at 5Gbps. DC operating point stabilizing is also considered in this paper. The proposed TIA is discussed mathematically and related simulations are performed in HSPICE using 0.18µm CMOS technology parameters. Results for the proposed TIA show the transimpedance gain of 42.1dBΩ, bandwidth of 3.6GHz, and power consumption of 12mW at 1.5V supply voltage. Also, Monte-Carlo analysis, noise analysis and effect of temperature variation on frequency response of the TIA are analyzed, which indicate that the proposed TIA is suitable to work as a 5Gbps TIA building block in an optical communication receiver system.
  • Saman Amini, Abolfazl Halvaei Niasar, Keyvan Amini Page 103
    In this study an improved direct torque control method (DTC) for Axial-flux hysteresis motor speed controlling is investigated. Time-consuming and dangerously of the necessity to manually adjust the motor speed and voltage when motor lagging occurs are the main drawback of the conventional control methods. The proposed method under acceleration and sequential braking on the Axial-flux hysteresis motor, based on the extracted modified motor dynamic equations in the Simulink Matlab environment has been simulated. As the results show, by using the proposed direct torque control method, the speed of the motor in the consecutive acceleration and braking process is controlled and the referral speed throughout the process operation with high accurate has been followed. Also this control system has shown that it is reliable method and stable against disturbances. Compared with conventional vector control methods, less complexity, higher speed and accuracy and easier implementation ability are significant features of the proposed method.
  • mehdi tabasi, Hosein Shaddel Page 111
    Transmission expansion planning (TEP) refers to specifying the place, time, and number of new transmission lines that should be established, so that given the network available, one can fulfill the potential demand of the power system in the future in terms of both operation and economic aspects (given the system constraints). Nevertheless, TEP is intrinsically a large-scale, mixed integer, nonlinear, and non-convex problem, which basically has several local optima. Solving this problem is very difficult and its computation is very time-consuming. To solve such a problem, a powerful optimization method is needed. In this paper, to solve the TEP problem, a new optimization algorithm called bacterial foraging optimization algorithm (BFOA) has been used. The proposed method has been studied on a 6-bus network for different scenarios, with the results indicating efficiency of BFOA.
  • Soorena Zohoori, Mehdi Dolatshahi Page 123
    In this paper, a one-bit ultra-low-power full adder cell using GDI structure is proposed. Main objective of this design is not only providing low power consumption, but also providing full swing outputs. In this paper, combination of different logics and stacking technique are used to provide an ultra-low power cell. Also, by using stacked inverters after each function, full swing characteristic for the cell is obtained. These characteristics are obtained in cost of more occupied chip area and higher delay. In order to verify the performance of the proposed cell, simulations are done in HSPICE using 90nm CMOS technology library. Beside Noise immunity, power consumption is also analyzed under different load conditions, different supply voltages and different temperatures. Although delay of the circuit is increased, results show a tremendous reduction in power consumption and an improved power-delay-product for the proposed full adder cell.
  • Meysam Azimi, Roein, Zahra Mostafavi Darani Page 131
    This paper presents the low noise amplifier for ultra wide-band applications.the UWB LNA is design in 0.18µm CMOS technique to achieve low noise figure ,low power consumption and high gain. To attain the low power dissipation and low supply voltage,foldedcascode with current reused technique is utilized in first stage. Negative feedback is adopted to extend the bandwidth. using the proposed technique ,a maximum gain of 12.7 dB and minimum noise figure of 2dB is achieved. The total power consumption is37 mW.S11 and S22 are less than -10 dB.