فهرست مطالب

Iranian Journal of Electrical and Electronic Engineering
Volume:17 Issue: 3, Sep 2021

  • تاریخ انتشار: 1400/01/24
  • تعداد عناوین: 13
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  • Z. Najafniya, Gh. Karimi*, Mahnaz Ranjbar Page 1626

    Neural synchronization is considered as a key role in several neurological diseases, such as Parkinson’s and Epilepsy’s disease. During these diseases, there is increased synchronization of massive numbers of neurons. In addition, evidences show that astrocytes modulate the synaptic interactions of the neuronal population. The Astrocyte is an important part of a neural network that can be involved in the desynchronization of the neuronal population. In this paper, we design a new analog neuromorphic circuit to implement the effect of astrocyte in the desynchronization of neural networks. The simulation results demonstrate that the astrocyte circuit as a feedback path can be desynchronized to a synchronized neural population. In this circuit, as a first step, the population of twenty neurons is synchronized with the same input currents. Next, by involving an astrocyte feedback circuit, the synchronization of the neural network is disturbed. Then, the neuronal population will be desynchronized. The proposed circuit is designed and simulated using HSPICE simulator in 0.35 μm standard CMOS technology.

    Keywords: Synchronization, Astrocyte, Neural Network, Analog Circuit
  • M. Ahmadi Jirdehi*, V. Sohrabi Tabar Page 1722

    Control center of modern power system utilizes state estimation as an important function. In such structures, voltage phasor of buses is known as state variables that should be determined during operation. To specify the optimal operation of all components, an accurate estimation is required. Hence, various mathematical and heuristic methods can be applied for the mentioned goal. In this paper, an advanced power system state estimator is presented based on the adaptive neuro-fuzzy interface system. Indeed, this estimator uses advantages of both artificial neural networks and fuzzy method simultaneously. To analyze the operation of estimator, various scenarios are proposed including impact of load uncertainty and probability of false data injection as the important issues in the electrical energy networks. In this regard, the capability of false data detection and correction are also evaluated. Moreover, the operation of presented estimator is compared with artificial neural networks and weighted least square estimators. The results show that the adaptive neuro-fuzzy estimator overcomes the main drawbacks of the conventional methods such as accuracy and complexity as well as it is able to detect and correct the false data more precisely. Simulations are carried out on IEEE 14-bus and 30-bus test systems to demonstrate the effectiveness of the approach.

    Keywords: Adaptive Neuro-Fuzzy System, Artificial Neural Network, False data, Load Uncertainty, State Estimation
  • S. Abolmaali* Page 1730

    Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.

    Keywords: Area Reduction, Gate Resizing, Path Sensitization, Timing Analysis, Viability Analysis
  • H. Shayeghi*, Y. Hashemi Page 1768

    The main idea of this paper is proposing a model to develop generation units considering power system stability enhancement. The proposed model consists of two parts. In the first part, the indexes of generation expansion planning are ensured. Also, small-signal stability indexes are processed in the second part of the model. Stability necessities of power network are supplied by applying a set of robustness and performance criteria of damping. Two parts of the model are formulated as two-objective function optimization that is solved by adaptive non-dominated sorting genetic method-III (ANSGM-III). For better decision-making of the final solution of generation units, a set of Pareto-points have been extracted by ANSGM-III. To select an optimal solution among Pareto-set, an analytical hierarchy style is employed. Two objective functions are compared and suitable weights are allocated. Numerical studies are carried out on two test systems, 68-bus and 118-bus power network. The values of generation expansion planning cost and system stability index have been studied in different cases and three different scenarios. Studies show that, for example, in the 68-bus system for the case of system load growth of 5%, the cost of generation expansion planning for the proposed model increased by 7.7% compared to the previous method due to stability modes consideration and the small-signal stability index has been improved by 6.7%. The proposed model is survived with the presence of a wide-area stabilizer (WAS) for damping of oscillations. The effect of WAS latency on expansion programs is evaluated with different amounts of delay times.

    Keywords: Planning, Stability, Wide-Area Damping, Generation
  • Z. Boudjema*, H. Benbouhenni, A. Bouhani, F. Chabni Page 1793

    This article presents the implementation of an improved space vector pulse width modulation  (SVPWM) technique based on neural network for a real two level voltage source inverter (VSI) realized in our Lab. The major goal of using this new technique is the amelioration of the voltage quality in the output of the VSI by decreasing the effect of the harmonics. The used technique has been simulated by MATLAB/Simulink and then implemented using a DSPACE card on a real two level VSI. The advantages of the used technique are shown by simulation and experiment results.

    Keywords: Space Vector Pulse Width Modulation, Two Level Voltage Source Inverter, Neural Network, DSPACE Card
  • S. K. Gudey*, S. Andavarapu Page 1857

    A three-phase dual-port T-type asymmetrical multilevel inverter (ASMLI) using two sources, solar forming the high voltage level and the battery forming the low voltage level, is considered for grid interconnection. A vertical shifted SPWM is used for the ASMLI circuit. A transformerless system for grid interconnection is achieved for a 100-kW power range. A well-designed boost converter and a Buck/Boost converter is used on the front side of the inverter. Design of battery charge controller and its controlling logic are done and its SOC is found to be efficient during charging and discharging conditions. A closed-loop control using PQ theory is implemented for obtaining power balance at 0.7 modulation index. The THD of the current harmonics in the system is observed to be 0.01% and voltage harmonics is 0.029% which are well within the permissible limits of IEEE-519 standard. The power balance is found to be good between the inverter, load, and the grid during load disconnection for a period of 0.15s. A comparison of THD’s, voltage, current stresses on the switches, and conduction losses is also presented for a single-phase system with respect to a two-level inverter which shows improved efficiency and low THD. Hence this system can be proposed for use in grid interconnection with renewable energy sources.

    Keywords: Asymmetrical Multilevel, Battery, Efficiency, Solar, THD
  • G. Morankar* Page 1914

    Tremendous developments in integrated circuit technology, wireless communication systems, and personal assistant devices have fuelled growth of Internet of Things (IoT) applications and smart cards. The security of these devices completely depends upon the generation of random and unpredictable digital data streams through random number generator. Low quality, low throughput, and high processing time are observed in software-based pseudo-random number generator due to interrelated data or programs and serial execution of codes respectively. In this paper, FPGA implementation of low power true random number generator through ring oscillator for IoT applications and smart cards is presented. Ring oscillators based on higher jitter and sampling techniques were exploited to present true random number generator. Further statistical parameters of the generated data streams are enhanced through feedback mechanism and post-processing technique. The presented true random number generator technique does not depend on the characteristics of a particular FPGA. The presented technique consumes low power, requires low hardware footprints and passes the entire National Institute of Standards & Technology (NIST) 800-22 statistical test suite. The presented low power and area true random number generator with enhanced security through post-processing unit may be applied for encryption/decryption of data in IoT and smart cards.

    Keywords: Random Number Generator, Ring Oscillator, Jitter, Low Power, IoT, Smart Cards
  • T. Agheb, I. Ahmadi*, A. Zakariazadeh Page 1916

    Optimal placement and sizing of distributed renewable energy resources (DER) in distribution networks can remarkably influence voltage profile improvement, amending of congestions, increasing the reliability and emission reduction.  However, there is a challenge with renewable resources due to the intermittent nature of their output power. This paper presents a new viewpoint at the uncertainties associated with output powers of wind turbines and load demands by considering the correlation between them. In the proposed method, considering the simultaneous occurrence of real load demands and wind generation data, they are clustered by use of the k-means method. At first, the wind generation data are clustered in some levels, and then the associated load data of each generation level are clustered in several levels. The number of load levels in each generation level may differ from each other. By doing so the unrealistic generation-load scenarios are omitted from the process of wind turbine sizing and placement. Then, the optimum sizing and placement of distributed generation units aiming at loss reduction are carried out using the obtained generation-load scenarios. Integer-based Particle Swarm Optimization (IPSO) is used to solve the problem. The simulation result, which is carried out using MATLAB 2016 software, shows that the proposed approach causes to reduce annual energy losses more than the one in other methods. Moreover, the computational burden of the problem is decreased due to ignore some unrealistic scenarios of wind and load combinations.

    Keywords: Correlation Modeling, Distribution System, Load Demand, Wind Turbine Allocation, Sizing
  • M. Mohiti, S. Sabzevari, P. Siano* Page 1945

    Islanding detection is essential for reliable and safe operation of systems with distributed generations (DG). In systems with multiple DGs, the interaction between DGs can make the islanding detection process more challenging. To address this concern, this paper proposes a two-stage islanding detection method for power systems equipped with multiple-DGs through estimation of high frequency impedance (Zf) and determination of the total harmonic distortion (THD). The impedances of the DGs are estimated at distinct frequencies to avoid interval overlaps. The concept of different frequency bands makes the proposed method applicable to multiple DG systems. To evaluate the effectiveness of the proposed method, a test system with multiple DGs is simulated through several case studies in PSCAD/EMTDC. The simulation results demonstrate the accuracy of the proposed islanding detection method in both single and multi-DG systems. It is also shown that the proposed method remains robust under different operating conditions and events.

    Keywords: Islanding Detection, Decentralized Method, High Frequency, Impedance Estimation, Multi-DG
  • H. Zahedi Abdolhadi, Gh. Arab Markadeh*, S. Taghipour Boroujeni Page 1955

    Classical structure of Doubly Fed Induction Generators (DFIGs) is not completely adapted in high-speed regions due to their brushes and slip rings. So in the Cascaded DFIGs (CDFIGs), the rotor windings of a given DFIG are supplied by another wound rotor induction machine leading to a complete brushless structure. This paper presents and compares Sliding Mode Control (SMC) and Terminal Sliding Mode Control (TSMC) methods to control the output voltage of CDFIG. The SMC and TSMC methods are identified as strong controllers with large stability and robustness margins. In this paper, the SMC and TSMC methods are evaluated and compared to the conventional Voltage Oriented Control (VOC) in terms of output voltage change, prime over speed’s variation, and nonlinear load. Simulation and experimental results using a TMS320F28335 based prototype system show that the SMC and TSMC techniques are more robust against parameter variations and uncertainties, and TSMC offers improved dynamic response.

    Keywords: CDFIG, SMC, TSMC, Nonlinear Load
  • H. Hamdoun, S. Nazir*, J. A. Alzubi, P. Laskot, O. A. Alzubi Page 1956

    High-Efficiency Video Coding (HEVC) is the latest video encoding standard that achieves much better compression efficiency compared to the earlier encoding standards. Satellite channels have a long round trip time (RTT) making it difficult to use packet acknowledgments. Real-time video streaming applications preclude such packet acknowledgments in satellite networks due to strict delay constraints.  We propose a combined use of Turbo Coding (TC) and Network Coding (NC) techniques to achieve better video quality over the noisy satellite links using UDP at the transport layer. We evaluate the performance improvement of turbo network coding (TNC-UDP) over the traditional turbo-coded (TC-UDP) protocol for HEVC video streaming in satellite networks. The simulation results show that compared to TC-UDP, the proposed scheme achieves PSNR improvements ranging from 14-20 dB for poor channel conditions (1-2 dB) for the two selected video sequences.

    Keywords: HEVC, Turbo Coding, Systematic Coding, Multimedia Streaming, Packet Loss
  • F. Rezaee Alam*, B. Rezaeealam, S. M. M. Moosavi Page 1965

    Poor modeling of air-gap is the main defect of conventional magnetic equivalent circuit (CMEC) model for performance analysis of electric machines. This paper presents an improved magnetic equivalent circuit (IMEC) which considers all components of air-gap permeance such as the mutual permeances between stator and rotor teeth, and the leakage permeances between adjacent stator teeth and adjacent rotor teeth in the air-gap. Since the conformal mapping (CM) method can accurately take into account the air-gap region, IMEC gets help from the CM method for calculating the air-gap permeance components. Therefore, the obtained model is a hybrid analytical model, which can accurately take into account the magnetic saturation in iron parts by using the CMEC, and the real paths of fringing flux, leakage flux, and the main flux in the air-gap by using the CM method. For a typical wound rotor induction motor, the accuracy of the results obtained by IMEC is verified by comparing them with the corresponding results determined through CMEC, improved conformal mapping (ICM), finite element method (FEM), and the experiment results.

    Keywords: Improved Magnetic Equivalent Circuit (IMEC), Conformal Mapping (CM), Conventional Magnetic Equivalent Circuit (CMEC), Magnetic Saturation, Permeance
  • N. Raj* Page 1972

    The performance of any system is decided by the circuit configurations used in its implementation. Current mirror is one of those circuit configurations which are widely used in analog system designs. The performance of current mirror is decided by its parameters which include large operating range, wide bandwidth along with very low input and very high output resistances. In this paper, a low voltage flipped voltage follower based current mirror is presented. The structure flipped voltage follower is initially modified using a feedback path which results in the low impedance node which when considered as input in the proposed current mirror results in an extremely low value of input resistance. Compared to conventional flipped voltage follower based current mirror design the proposed design works well with minimum error in microamperes range with extended bandwidth without affecting its output resistance. The input resistance gets scaled down to 17 ohms from 840 ohms whereas bandwidth gets almost doubled approximately to 4.5GHz from 2.4GHz. The power dissipation ranges in microwatts. The simulations are supported with mathematical analysis. The complete analysis is done in HSpice using MOS models of 0.18-micron technology at a dual supply voltage, ±0.5V.

    Keywords: Current Mirror, Flipped Voltage Follower, Input Resistance, Output Resistance, Bandwidth