نشریه مهندسی مخابرات جنوب
پیاپی 39 (بهار 1400)

Common methods of reducing signal distortion received at the output of telecommunication systems are generally based on linear methods. These methods have many limitations, including the inability to remove the noise inside the band. The purpose of this paper is to reduce distortion and reconstruction of received weak signal and pull it out of the noise sea. In this paper, we employed averaging method to reduce distortion and improve the received signal. The analysis is performed and simulated in several scenarios and results show that in a certain number of channels, increasing the number of repetitions usually increases the signal to noise. Also, as the amplitude decreases in different experiments, the signal-to-noise decreases with constant repetitions. If the received signal amplitude is more than half of the noise amplitude, the main signal is extracted. However, if the signal amplitude is less than half of the noise amplitude, the main signal will not be extracted.

This paper presents a broadband low noise amplifier (Low Noise Amplifier is the first block in a post-antenna telecommunication receiver and its role is to amplify the weak signal received by the antenna by adding minimum noise to it, thereby minimizing signal-to-noise ratio (SNR).)using a new technique to optimize the linearity and third order harmonic effect. The third order distortion elimination technique was performed using the transistor body effect in a common gate differential amplifier, while the amplifier investigated compared to previous work improved the power consumption in addition to IIP3. Cadence IC Design tools and 130 nm technology were used for the simulation. Simulations show that the circuit has reached a minimum noise value of 68.3 dB and a gain of 19.15 dB. It also has a power consumption of 9 mW, while the circuit uses a 1.2V power supply. IIP3 is also achieved at 6GHz at 20MHz, with a frequency of 1.9 dBm.

In this paper, a fully differential successive approximation A/D converter is presented using the extended non-binary search algorithm with an accuracy of 10-bits, 11 comparison steps, and the sampling rate of 4.17MS/s which is suitable for low-power applications because it does not require to be calibration. In the non-binary search algorithm, there are overlaps between the search rang, that allow comparison decision errors to be digitally corrected. To improve the linear behavior of the proposed structure, a capacitive array D/A converter with non-binary weight is implemented, and the sampling frequency is increased compared to the conventional successive approximation converter through proper selection of non-binary capacitances of the capacitive array. The proposed structure operates based on monotonic switching logic. This switching method reduces the power consumption of DAC compared to conventional switching. The proposed structure is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, signal to noise and distortion ratio (SNDR) is 61.35dB, power consumption is 78.14µW, and figure of merit is 19.57(fj/Conv.step).

Nowadays, digital images are widely used in the diagnosis of disease, facial and fingerprint, security systems, and more. Therefore, providing an accurate algorithm in image recognition and retrieval is very important. This paper presents a combination of PCA and LDA methods for image retrieval. In this method, first, the color images in the RGB space are transferred to the HSV space, then the color, shape, and texture properties are extracted from the "V" component of the HSV color space. The proposed feature vector is then constructed using the LDP histogram, color histogram, Tamura histogram, and common event matrix. Then, by combining the two methods of PCA and LDA, the specificity is reduced and finally, the classification is done. Four scenarios were designed and evaluated to evaluate the proposed method. According to experimental result and evaluation criteria, The accuracy obtained was 97.6 which indicates the proper performance of the proposed method compared to similar tasks.

Social propositional systems are a new generation of systems that use the social network as a user modeling platform to maximize some challenges by using rich interactive data volumes. To make Social networking sites offer new friends to registered users based on local graph features. The main purpose of the link prediction problem on social networks is to suggest a list of users to a particular user that they will probably be communicating in the future. In this research, a prediction method for the link is presented based on the characteristics of classification models. Here, the prediction problem of the link is transformed into a classifying problem with two positive and negative classes, where the positive class represents the relationship and the negative class indicates that the two users are not communicating. Three classical classes DT, NN and NB are used for classification work. To create the dataset, the features of credibility, optimism, number of neighbors, the number of paths of different lengths, the number of shared tweets, the number of internal and external axes are used. Although self-centered grids do not have much overlap in the rings, experiments show that the consideration of self-directed pathways significantly improves predictive performance. The DT classification has recorded the best performance with an average accuracy of 99.85%.

In this paper, while describing the operation of the ADC SAR, we examine the blocks that make up this converter and the share of each of the circuits is in total power consumption and tried to reduce the power consumption. Since the DAC and comparator respectively have the highest power consumption in this type of converter, most designers pay attention to the two sides to reduce power consumption. DAC design is more important from these two circuits, so an analog to digital converter with the fully differential is proposed with a proposed switching method to reduce the power consumption of the DAC. In this converter, the energy consumed DAC has fallen by 86% compared to conventional structure and has decreased by 24.65%compared to the monotonic structure. Due to the performance of the DAC complement switching of the upper and lower half-circuits, caused the voltage variations of the common-mode inputs of the comparator to be constant from step two to the next, and this improves the constant of the voltage variation of the common mode of our circuit deflection Which is the benefits from this proposed method. All simulation in the 0.18 μm CMOS technology with 1.8-V power supply is done.