Majlesi Journal of Telecommunication Devices
Volume:2 Issue: 3, Sep 2013

In this paper, a new dual-frequency LC oscillator is introduced. This new architecture is designed taking the advantage of a Wheatstone-bridge LC resonator concept that enables the oscillator to generate two different frequencies simultaneously. In contrast to previous designs, no transistor switches are incorporated in the structure of this dual-frequency circuit. So, the proposed configuration is suitable for low phase noise applications. The performance of the oscillator has been verified using circuit simulations in 0.18 µm CMOS technology. Circuit simulations show phase noises of -109 dBc/Hz and -105 dBc/Hz for 1.8 GHz and 2.7 GHz frequency bands respectively in 100 kHz offset frequency.

This article is organized to represent the work specifications of micro electro mechanical gap-tuning capacitors and to increase the both of tuning range and quality factor, a three-plate capacitor which can be fabricated in standard 0.18 μm CMOS technology is designed and simulated. The simulation of the capacitor was done using the EM3DS software and the simulation results show tuning range of 100%, that is 2 times higher than tuning range of the conventional parallel plate capacitor. The plates of this capacitor are designed by using the available metal layers in the TSMC 0.18 μm CMOS technology that have caused decreasing the series resistance and increasing the quality factor to 300 in 1 GHZ.

The design and layout of a printed circuit board is crucial to the functionality and electromagnetic compatibility (EMC) performance of the product. The proper layout in printed circuit boards must satisfy EMC requirements in board level and system level. Some of these requirements is about placement of components, board partitioning, trace routing and return path continuity. Designers must have strict control on these mentioned requirements. In this paper we study these cases and present their relevant design notes. Also we provide design points about electromagnetic compatibility requirements of the power and supply system, shielding, digital and analog circuits on printed circuit boards. They are all must be considered to meet emission and susceptibility requirements of the PCB.

All oscillators are periodically time varyingsystems, so to accurate phase noise calculation andsimulation, time varying model should be considered. Phasenoise is an important characteristic of oscillator design anddefined as the spectral density of the oscillator spectrum atan offset from the center frequency of the oscillator relativeto the power of the oscillator. Linear time invariant (LTI) andlinear time variant (LTV) model’s for calculating phase noisein ring oscillator is discussed. In this paper a new techniquebased on LTV model for impulse sensitivity function (ISF)calculation and thus phase noise estimation inCMOS single-ended ring oscillator is presented. This methodis simpler than other methods and ISF can be simulated andcalculated easily. Good results between theory and simulationis observed.

In this paper a low-noise low-power CMOS operational transconductance amplifier (OTA) using dynamic threshold voltage MOSFET (DTMOS) technique is presented. The OTA is designed and simulated using 0.18 µm CMOS technology. The performed simulation results show an input-referred noise of 520.2 nV/√Hz at 1 mHz so reduces to 115.8 pV/√Hz at 1 Hz, and a power consumption of 191.9 nW under 5 pF loads. The dc open loop gain is 53.13 dB, a phase margin of 50o and a unity gain-bandwidth (UGB) of 572.9 kHz while operating at 0.8 V supply voltage. The proposed OTA is suitable for low noise and low-power application such as medical application

In this paper, we have proposed a distributed power control algorithm to reduce interference and then outage probability in a heterogeneous cellular network based on Poisson point process (PPP) model. For adjusting of power, we have considered m tier outage probability in which introduces outage probability for macro user located on origin that femto BSs creates interference for him. Our study has done on network with K-tiers being modeled as independent Poisson point processes. Simulation results confirm mitigation of outage probability using proposed power control algorithm in this model.

In recent years, a variety of communications systems based on chaos and nonlinear dynamics have been proposed. However, most of these algorithms not working under realistic channel conditions. This paper presents a channel equalization scheme for chaotic communication systems based on a Logistic Chaos map. The dynamic representation of Logistic map is exploited to allow a straightforward and efficient implementation. Equalizer filter coefficients are updated using a new combination of RLS and LMS by partitioned the main frame of data into subsequent frames, the first frame which include the training sequence is fed to RLS for better convergence speed, however switch to LMS for low complexity.

Real-time spectrum sensing with precise accuracy is the most important step to establish cognitive radio networks (CRNs). Detecting the presence of primary users (PUs) that use DS-CDMA (Direct sequence code division multiple access) technique is a challenge for the secondary users (SUs) in CRNs. DS-CDMA transmissions with very low signal to noise ratio (SNR) results in a signal hidden below the noise level, therefore, the existing classic detection methods are not effective enough to sense the signals. In this paper, a method is proposed to resolve this challenge. The proposed method based on fluctuation of correlation estimators searches on a specific frequency band and detects primary user''s signals. Simulation results show that the sensing performance of the method is better than other conventional schemes for dealing with DS-CDMA users.