نشریه صنایع الکترونیک
پیاپی 4 (زمستان 1389)

An important problem for the WiMAX networks is how to provide a guaranteed quality of service for applications. A key aspect of this problem is how BSs should share bandwidth capacity between different classes of traffic. This decision needs to be made for each incoming packet, and is known as the packet scheduling problem. A major challenge in packet scheduling is that the behavior of each traffic class may not be known in advance, and can vary dynamically. In this paper, we describe how we have modeled the packet scheduling problem as an application for reinforcement learning (RL). We demonstrate how our RL approach can learn scheduling policies that satisfy the quality of service requirements of multiple traffic classes under a variety of conditions. The proposed solution has been designed to have an ability to accommodate integrated traffic in the networks with effective scheduling schemes. A series of simulation experiments have been carried out to evaluate the performance of the proposed scheduling algorithm. The results reveal that the proposed solution performs effectively to the integrated traffic composed of messages with or without time constraints and achieves proportional fairness among different types of traffic.

The sinuous antennas have a numerous applications in military and civil systems such as direction finding, research and measurement laboratories and reflector feeds; which are due to their superior broadband characteristics and simultaneous right and left hand circular polarization. These capabilities are most required in radars and aerospace applications. Although, the sinuous antenna size, bandwidth, and radiation parameters are the same as spiral antenna, due to complex structure and complicated feeding network, the sinuous parameters do not investigated accurately. In this paper, a comprehensive survey on the antenna parameters has been proposed. Based on these studies, design, construction and measurements of an optimized planar sinuous antenna for 1–5 GHz frequency range have been presented.

In this paper, according to the size of the transistors and the feedback gain of the oscillator, a design point in which the gain of the active core of the oscillator is maximum, is derived. In order to realize the feedback gain, we utilize a transformer. This transformer is employed in such a way that it could be able to provide the feedback gain for the oscillator and also eliminate the large portion of parasitic capacitance, simultaneously. By using this technique, the phase noise at 1MHz offset and the tuning range in comparison with the general transformer oscillator is improved by 5dB and 70% respectively. Furthermore, we show that with linearization of the oscillator in millimeter-wave frequencies, phase noise of the oscillator can also be reduced even more. Regarding this criteria we linearize the oscillator as much as possible. Post-simulation results show that the circuit designed in 0.18-μm CMOS technology, consumes 43mW while showing -89dBc/Hz phase noise at 1MHz offset with 1.9GHz tuning range around 57GHz.

LEO satellites orbit very fast respect to the Earth stations, so the tracking of these satellites is important. But due to some challenges, such as structural deformations caused either by loads or by the temperature gradient, atmospheric distortion, or azimuth track unevenness, the position of beam is slightly different from the antenna position as measured by the encoders. Thus, the monopulse technique as the most accurate type of Auto-tracking techniques is used and analyzed. Also, the reduction of beam error and increment of received power versus signal to noise ratio are investigated. Finally, estimation parameters such as variance, mean and RMSE of monopulse technique versus signal to noise ratio are investigated.

In this paper, a new feeding structure is applied in the patch antenna design to overcome undesirable features of the earlier multilayer feeding structures while maintaining their interesting features. To more readily understand the operation mechanism of proposed feeding structure, an efficient circuit model has been also presented. It is known that proximity and aperture coupled feeding structures are sensitive to the transverse feed point location. In contrast, the proposed feeding architecture is very easy to fabricate and it overcomes the alignment difficulties arising from the proximity and aperture coupled feeding structures. The CST simulation results, analytic results and measurement ones show good agreement with each other. Moreover, a new miniaturization technique which is based on using High Impedance Wire (HIW) structures has been introduced. Due to their artificial high permeability properties, using proposed method, someone may miniaturize conventional patch antenna without bandwidth and efficiency corruption. Applying suggested method to the proposed antenna structure, two different feeding structures have been designed and compared. Finally, by using AMC structures to load HIW, more miniaturization factor has been achieved.

In this paper a Time-Amplifier, one of the most significant blocks of the time domain signal processing modules will be designed and simulated. Time domain signal processing is one of the most forerunner alternatives for the amplitude domain signal processing specially in nowadays nanotechnology devices. The main core of a time mode processor is a Time-to-Digital Converter (TDC). Increasing the resolution of the TDC, the processing of the signal is performed with higher quality. One of the most challenging efforts is the processing of two signals with very small time difference between their edges. Recently, some new techniques are proposed to overcome this significant problem. One of these techniques is amplifying the time difference, before employing it into the time mode signal processor or a TDC. Regarding this bottleneck, in this paper a high resolution, high gain, highly linear time amplifier (TAMP) with a large dynamic range (DR) is designed. The pre-detector of this TAMP, is a novel digital Pulse-to-Edge Converter (PEC) which also can operate in high frequencies. This TAMP is utilized in a proposed TDC in order to give one important utility of the circuit. The proposed topology is designed in a 0.18μm CMOS process and simulated via ADS2009 and Cadence® (Spectre RF). The simulation results illustrates the total power consumption is 1.7 mW, occupied area of the chip is below 0.35 mm2, time resolution is 5 psec, gain of the TAMP is approximately near to 200 s/s and the total linear DR of the TAMP is almost 350 psec.

In this paper, using a new approach and vision, with a modern architecture for digital images processing on the hardware is presented. One of the biggest disadvantages of hardware solutions for use instead of software systems, is their lack of flexibility, However; other important parameters such as reliability and speed of their performance in the design are very attractive. In this paper partial dynamic reconfiguration technique as a new way to solving this issue is recommended. This paper by exhibition a new architecture based on partial reconfiguration can implement several different filters for real-time digital images processing on hardware. Using this technique, can be achieved to real-time digital images processing at low power consumption, high efficiency and high speed on the FPGA. Proposed architecture written by the VHDL standard hardware description language and then implemented on the FPGA. Observation simulation, synthesis and implementation results will shown that proposed architecture have high efficiency, high speed processing, low power consumption and less utilized space. Benefits of the proposed architecture eliminates, hardware processing bottlenecks such as processing speed and real time industrial processing and possible it’s utilization in the industrial and medicine.