Sub-Threshold 8T SRAM Cell with Improved Write-Ability and Read Stability

Conventional 6T SRAM cell suffers from poor write-ability and poor read stability at low supply voltages. In this paper a new 8T SRAM cell is proposed that achieves improved write-ability and increased read stability at the same time. The proposed SRAM cell can successfully operate at small supply voltages as low as 275 mV whereas conventional 6T SRAM cell cannot. To show the prominence of the proposed cell and for better comparison, our SRAM cell, conventional 6T SRAM cell, and also three other SRAM cells from recent literature are designed in a 90nm industrial CMOS technology with the same conditions. Simulation results show that the proposed 8T SRAM cell decreases write and read delays by 47.5% and 50%, respectively at supply voltage of 800 mV. Our SRAM cell also improves power consumption for single write operation by 40% over the best design at supply voltage of 800 mV. Among the five designs compared, our design is the only one that operates at supply voltages as low as 275 mV. Finally, layout of the proposed SRAM cell is developed in 180 nm industrial CMOS technology and results of post-layout simulations are discussed.