Analysis and Expansion of a Compact Model of Propagation Delay Time for Nano-CMOS NAND Gates in Response to Statistical Variability of Fabrication

With shrinking transistor dimensions into nano meter scale, electrical parameters of transistors become more sensitive against statistical or random variations. Moreover, accurate estimation of these variations using “atomistic simulators” is time consuming and not a cost effective approach. In this paper for the first time, analytical models have been used to study the impacts of statistical variability of fabrication process on propagation delay time in a 35 nm CMOS NAND gate. With selecting appropriate set from analytical model’s parameters, the impact of statistical variability on the propagation delay time have been modeled and extended. Moreover, target analytical model has been benchmarked against statistical variability of fabrication process. The results obtained from extension of this model have been compared with the accurate atomistic simulations. It is observed that by applying different sets of parameters the maximum error of propagation delay time reaches to 8.7% against accurate atomistic simulations but by applying our proposed approach, Standard Deviation (SD) error of propagation delay is estimated to 2.4%. Also the SD error of propagation delay reaches to 9.9% when normal regenerated parameters have been used. Eventually using proposed algorithm which encompasses regenerated Gaussian parameters while taking the correlation factor into account, the SD error decreases to 1.6%.