computer arithmetic

As an emerging technology, reversible computing enables the development of high-performance computing systems with low energy consumption. A residue number system (RNS) that performs arithmetic operations in parallel with error tolerance and no carry propagation requires forward and reverse converters to communicate with other digital circuits. Designing reversible forward and reverse converters using new technologies is very important due to their wide applications in implementing the RNS. These converters, which are the overhead of the system, increase energy consumption. This study proposes a hybrid converter conforming to reversible logic for the RNS. This hybrid converter unifies forward and reverse converters by sharing hardware and reversible gates. By using the mixed-radix conversion (MRC), the reverse conversion arithmetic relations adopt a similar format to that of the forward conversion arithmetic relations, and by the addition of a number of Fredkin gates and modifying the inputs, the reverse converter hardware is used to perform forward conversion. Based on the findings, the hybrid converter, which conformed to reversible logic for the moduli set {2^2n,2^n-1,2^(n+1)-1} and {2^n-1,2^n+1,2^2n+1}, decreased the quantum cost to 19.56% and 19.52%, respectively.

Residue number system (RNS) is considered as a prominent candidate for high-speed arithmetic applications due to its limited carry propagation, fault tolerance, and parallelism in “Addition”, “Subtraction”, and “Multiplication” operations. Whereas, “Comparison”, “Division”, “Scaling”, “Overflow Detection” and “Sign Detection” are considered as complicated operations in residue number systems, which have also received a surge of attention in a multitude of publications. Efficient realization of Comparators facilitates other hard-to-implement operations and extends the spectrum of RNS applications. Such comparators can substitute the straightforward method (i.e. converting the comparison operands to binary and comparing them with wide word binary comparators) to compare RNS numbers. Dynamic Range Partitioning (DRP) method has shown advantages for comparing unsigned RNS numbers in the 3-moduli sets {2^n,2^n±1} and {2^n,2^n-〖1,2〗^(n+1)-1}, in comparison with other methods. In this paper, we employed DRP components and designed a unified unit that detects the sign of operands and also compares numbers, for the 5-moduli set γ={2^2n,2^n±1,2^n±3}. This unit can be used for comparison of signed and also unsigned RNS numbers in the moduli set γ. Synthesized comparison results reveal 47% (54%) speed-up, 35% (32%) less area consumption, 25% (24%) lower power dissipation, and 60% (65%) less energy for n=8 (16) in comparison to the straightforward signed comparator. According to the results of this study, DRP method for sign detection and comparison operations outperforms other methods in different moduli sets including 5-moduli set γ={2^2n,2^n±1,2^n±3}.

The 4-moduli set residue number system (RNS), , with a wide dynamic range, has recently been proposed as a balanced 4-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this 4-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite 14.7 tool and the Spartan6 family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a 46% and 28% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.