parallel processing

Residue Number System is a kind of numerical systems that uses the remainder of division in several different moduli. Conversion of a number to smaller ones and carrying out parallel calculations on these numbers will increase the speed of the arithmetic operations in this system. However, the main factor that affects performance of system is hardware complexity of reverse converter. Reverse converters convert the resulted remainders to the conventional number system. In this paper an area efficient reverse converter is proposed for moduli set {2^n+1,2^n-1,2^n} based on two-part RNS and mixed radix conversion algorithm. Selecting appropriate order of modulus and using well-known lemmas, leads to reduce the complexity of the proposed converter comparing to previous designs. To have an accurate comparison, both unit gate model and simulation in Xilinx 13.1 FPGA are used in this paper. The results of comparison indicate that the novel proposed reverse converter has improved the time complexity and area, while having almost same delay.

Residue Number System is a numerical system which arithmetic operations are performed parallelly. One of the main factors that affects the system’s performance is the complexity of reverse converter. It should be noted that the complexity of this part should not affect the earned speed of parallelly performed arithmetic unit. Therefore in this paper a high speed converter for moduli set {2n-1, 2n -1, 2n} is proposed which is based on Two-Part RNS and Chinese Reminder Theorem. Using this method has increased the speed of reverse converter. To have an accurate comparison both unit gate model and synthesized silicon tools are used and their parameters are compared in terms of delay and area. Converters are implemented in hardware description language and correctness for various n values are verified by simulation and execution on Cadence. As the results show, the proposed circuit has lower delay by around 21% in comparison to previous presented converter.

This paper aims to introduce an effective classification method of learning for partitioning the data in statistical spaces. The work is based on using multi-constraint partitioning on the stochastic learning automata. Stochastic learning automata with fixed or variable structures are a reinforcement learning method. Having no information about optimized operation, such models try to find an answer to a problem. Converging speed in such algorithms in solving different problems and their route to the answer is so that they produce a proper condition if the answer is obtained. However, despite all tricks to prevent the algorithm involvement with local optimal, the algorithms do not perform well for problems with a lot of spread local optimal points and give no good answer. In this paper, the fusion of stochastic learning automata algorithms has been used to solve given problems and provide a centralized control mechanism. Looking at the results, is found that the recommended algorithm for partitioning constraints and finding optimization problems are suitable in terms of time and speed, and given a large number of samples, yield a learning rate of 97.92%. In addition, the test results clearly indicate increased accuracy and significant efficiency of recommended systems compared with single model systems based on different methods of learning automata.

The IP Lookup Process is a key bottleneck in routing due to the increase in routing table size, increasing traffic and migration to IPv6 addresses. The IP address lookup involves computation of the Longest Prefix Matching (LPM), which existing solutions such as BSD Radix Tries, scale poorly when traffic in the router increases or when employed for IPv6 address lookups. In this paper, we describe a high performance parallel IP lookup mechanism based on distributed memory organization that uses P processor for solving LPM problem. Since multiple processors are used, the number of prefixes to be compared for each processor has been reduced. In other words each processor needs to find LPM for a specific IP address among N/P of prefixes. In order to reduce the number of memory access in each processor which is a major bottleneck in IP lookup process, we use ISCB-Tree data structure for the sake of storing the forwarding table in each processor. ISCB-Tree is a B-Tree like data structure that reduces the height of prefix tree and logarithmic growing manner with the increasing number of prefixes. By the using of this data structure the number of memory access reduces sharply.