fpga implementation
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در سامانه های ردیابی هدف، از فیلتر ردیابی برای تخمین پیاپی و هموار موقعیت و سرعت هدف متحرک با کمینه خطا استفاده می شود. در این مقاله، روشی برای طراحی و پیاده سازی سخت افزاری فیلتر کالمن در چنین کاربردی ارائه شده است. روش پیشنهادی شامل یک پیاده سازی ممیز ثابت فیلتر روی FPGA است که در آن سرعت اجرای الگوریتم از طریق موازی سازی عملیات غیر وابسته بهبود یافته است. پس از طراحی بر اساس مساله داده شده، نسخه های ممیز شناور و ممیز ثابت فیلتر شبیه سازی و نسخه ممیز ثابت روی سخت افزار پیاده سازی شده است. برای ارزیابی کارایی فیلتر، داده های فاصله -سرعت یک هدف متحرک با مدل مناسب تولید و پس از چندی سازی و درآمیختن با اغتشاش به فیلتر اعمال می شوند. نتایج نشان می دهد که با انتخاب طول بیت مناسب، فیلتر پیاده سازی شده سریع و کارآمد بوده و با زمان اجرای حدود µs 4/0، موجب dB 11 کاهش در خطای تخمین فاصله شده و عملکردی نزدیک به نمونه ممیز شناور فراهم می آورد.
کلید واژگان: فیلتر کالمن، پیاده سازی FPGA، ردیابی، تخمین فاصله، تخمین سرعتTracking filters are extensively used within object tracking systems in order to provide consecutive smooth estimations of position and velocity of the object with minimum error. Namely, Kalman filter and its numerous variants are widely known as simple yet effective linear tracking filters in many diverse applications. In this paper, an effective method is proposed for designing and implementation of a Kalman filter in an object tracking application. The considered tracking application implies the capability to produce a smooth and reliable output stream by the tracking filter, even in presence of different disturbing types of noise, including background or spontaneous noises, as well as disturbances with continues or discrete nature. The presented method includes a fixed-point implementation of the Kalman filter on FPGA, which targets the joint estimation of position-velocity pair of an intended object in heavy presence of noise. The execution speed of the Kalman algorithm is drastically enhanced in the proposed implementation. This enhancement is attained by emphasis on hardware implementation of every single computational block on the one hand, and through appropriate parallelization and pipelining of independent tasks within the Kalman process on the other hand. After designing the filter parameters with respect to the requirements of a given tracking problem, a floating-point model and a fixed-point hardware model of the filter are implemented using MATLAB and Xilinx System Generator, respectively. In order to evaluate the performance of the filter under realistic circumstances, a set of appropriately defined scenarios are carried out. The simulations are carefully designed in order to represent the extremely harsh scenarios in which the input measurements to the filter are deeply polluted by different kinds of noises. In each simulation the position-velocity data corresponding to a moving object is generated according to an appropriate model, quantized, and contaminated by noise and fed into the filter. Performances of the Kalman filter in software version (i.e. the floating point replica) and hardware version (i.e. the fixed-point replica) are quantitatively compared in the designed scenario. Our comparison employs NMSE and maximum error values as quantitative measures, verifying the competency of our proposed fixed-point hardware implementation. The results of our work show that, with adequate selection word length, the implemented filter is fast and efficient; it confines the algorithm execution time to 50 clock pulses, i.e. about 0.4 µs when a 125 MHz clock is used. It is also verified that our implementation reduces the position and velocity estimation errors by 11 dB and 1.2 dB, respectively. The implemented filter also confines the absolute values of maximum error in position and velocity to 10 meter and 0.7 meter/sec. in the considered scenario, which is almost resembles the performance of its floating point counterpart. The presented Kalman filter is finally implemented on Zc706 evaluation board and the amount of utilized hardware resource (FFs, LUTs, DSP48, etc.) are reported as well as the estimated power consumption of the implemented design. The paper is concluded through comparison of the proposed design with some recent works which confirms the efficacy of the presented implementation.
Keywords: Kalman filter, FPGA implementation, Tracking, Distance estimation, Velocity estimation -
This paper presents a hardware implementation of both Hodgkin-Huxley (HH) and Leaky Integrate and Fire (LIF) spiking neuronal models. FPGA is used as digital platform due to flexibility and reconfigureability. The proposed neural models are simulated by MatLab and the results are compared with the HDL software’s output in order to evaluate the design. Simple architecture uses two counters and a comparator used as the main part of leaky Integrate and Fire model. For the Hodgkin and Huxley model a Look Up Table based structure is utilized. Although it consumes large amount of area, it results more reasonable propagation delay time hence higher operating frequency. The proposed architectures are evaluated on Stratix III device using Quartus II simulator. Maximum operating frequency of 583 MHz (limited to 500 MHz due to the device port rate) and 76 MHz are achieved for the LIF and HH architectures respectively.Keywords: Spiking neural network, LIF Model, HH Model, FPGA implementation
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Character recognition is very useful in various fields of engineering applications. Due to visual remarkable ability of humans, this paper describes a simple biological inspired model based on Spiking Neural Network (SNN) for recognizing characters. Two datasets are used: MNIST for recognizing English characters and Bani Nick Pardazesh dataset for recognizing Persian characters. The proposed network is a two layered structure consisting of Integrate and Fire (IF) and active dendrite neurons. In order to train first layer of this network, a proposed algorithm based on k-means is used. Furthermore, a modified algorithm based on Spike Time Dependent Plasticity (STDP) is used in order to train second layer of this network. This structure is designed in way that can be implemented on Field Programming Gate Array (FPGA) properly. Implementation results demonstrate that this model occupies not many resources and also it is very fast in character recognition applications. Finally by applying test data, the proposed neural structure has been evaluated. Simulation results indicate high accuracy of recognizing characters.Keywords: Character Recognition, Spiking Neural Network, STDP, k, means, FPGA Implementation
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A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The results we obtained show that with G = 55 our proposed design is able to compute GF(2163) elliptic curve scalar multiplication in 9.6 μs with the maximum achievable frequency of 250 MHz on Xilinx Virtex-4 (XC4VLX200), where G is the digit size of the underlying digit-serial finite field multiplier. Another implementation variant for less resource consumption is also proposed. With G=33, the design performs the same operation in 11.6 μs at 263 MHz on the same platform. The results of synthesis show that in the first implementation 17929 slices or 20% of the chip area is occupied which makes it suitable for speed critical cryptographic applications while in the second implementation 14203 slices or 16% of the chip area is utilized which makes it suitable for applications that may require speed-area trade-off. The new design shows superior performance compared to the previously reported designs.Keywords: Elliptic Curve Cryptography, Scalar Point Multiplication, FPGA Implementation, Finite, Field Arithmetic
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