secure hash algorithm

Secure Hash Algorithms (SHA) are essential parts of cryptographic algorithms that with advent of applications such as using PDAs in our society, their importance has increased dramatically in order to preserve confidentiality. Besides that, with technology development, the necessity of implementation of such algorithms on flexible platforms can be challenging. Therefore, using fewer resources and increasing the speed of operations are the main challenges in designing and implementing such algorithms. In this paper, a new architecture is proposed for FPGA-based processor for cryptographic algorithms SHA-2. In proposed processor, using memory units and multiport datapath and followed by parallel performance of processor reduces use of resources and increases data process speed. Processor architecture is modeled by VHDL language for SHA-2 and its implementation has been done on FPGA platforms for Virtex series by ISE software. The results of implementation indicate that the proposed processor compared with earlier works with similar objectives, was able to preserve desired level of throughput and efficiency by increasing 25% frequency for SHA-256 and occupying 55% less area for SHA-512. Proposed processor is appropriate for applications such as Trusted Mobile Platforms (TMP), Digital Currencies (Bitcoin) and secure routing of Networkon Chip (NoC).