cache

In recent years, electronic devices such as laptops, computers, smart mobile phones and other smart electronic devices have greatly increased, and all these electronic devices use one or more processors inside them, which according to the type of architecture of each processor may have different vulnerabilities. In this paper Investigation and evaluation of side channel vulnerabilities based on the vulnerabilities of Intel and ARM processors has been done based on the hierarchical analysis method. Based on the existing vulnerabilities, the attacks have been divided into 6 general categories, which have been evaluated based on indicators such as time, possibility, effectiveness, and cost. Among the 6 attacks investigated, 3 time-based attack, power side channel attack with software measurement and cache-based attack have respectively assigned the most points based on the evaluation criteria and the power side-channel with hardware measurement attack has the lowest score, where the overall mismatch rate is 0.06, which is acceptable. Also, 3 sub-criteria of key (password) recovery percentage, access level and covert channel ability have had the greatest impact on decision options. Finally, in addition to the overall ranking, these options are also scored based on each of the criteria. From the time point of view, the time-based attack and the power side channel attack with hardware measurement have the highest and the lowest priority, respectively, and from the possibility point of view, the time-based attack and the power side channel attack with software measurement have the highest and lowest priority, respectively. Also, from the effectiveness point of view, time-based attack and side-channel power attack with hardware measurement have higher and lower priority, respectively, and from the cost point of view, time-based attack and micro-architecture-based attack have the highest and lowest points and priority, respectively. Next, the risk level of these 6 strategies was scored and ranked using the CVSS parameter. The results of this evaluation show that 3 time-based attacks, micro-architecture-based attacks, and cache-based attacks, respectively, are more dangerous for the victim and will cause the most damage.

The modern processors that consist of large caches are very vulnerable to transient errors. Due to the importance of this problem, coding methods are adopted for protection against errors. The cost of reliability should be incurred to optimize the use of energy and area. This paper proposes an approach to dependability enhancement in unprotected caches of processors. For this purpose, the low-cost tag error mitigation mechanism is adopted to analyze the reliability of caches in modern processors. Benefiting from the tag Hamming distance increase technique, the proposed approach has a much lower overhead and decreases the false hit rate to zero.

Since multiple memory accesses are time consuming, processors use cache to optimize runtime. The cache leads to temporal changes in the implementation of a program and is one of the most important source of information leakage in the timing side channel. Flush+Reload attack is a series of Cache Side Channel attack that the most important characteristics of this attack can be used to identify access to a particular memory line and target being the lowest level cache (LLC) noted that these features lead to increased precision of attack and its usability. In this paper, a new Flush+Reload attack (of the chosen plaintext attack) on the AES implemented in the OpenSSL is presented. While the previous Flush+Reload attack on AES requires about 400000 encryption operations, the attack presented in this paper, required only about 100 encryption operations to fully recover encryption keys. The attack described in this paper is implemented in practice and the actual results confirm the attack’s integrity.