An Approach to Dependability Enhancement of Cache Memories

The modern processors that consist of large caches are very vulnerable to transient errors. Due to the importance of this problem, coding methods are adopted for protection against errors. The cost of reliability should be incurred to optimize the use of energy and area. This paper proposes an approach to dependability enhancement in unprotected caches of processors. For this purpose, the low-cost tag error mitigation mechanism is adopted to analyze the reliability of caches in modern processors. Benefiting from the tag Hamming distance increase technique, the proposed approach has a much lower overhead and decreases the false hit rate to zero.