fpga

Due to the increase in satellite-based positioning applications and their importance in daily life, the need for high-sensitivity receivers to acquire weak signals in limited environments such as tunnels, environments with tall buildings and streets between them, and similar things seems necessary. In a software receiver, the first and most important step is the acquisition of GPS signals. The purpose of this step is to determine the visible satellites and find the approximate values of the carrier frequency and code delay of the signals sent from the satellites. GPS receivers in weak signal conditions often face the problems of Doppler code and navigation data bit sign transition, which reduce the output SNR of the acquisition stage. One of the new methods that can overcome the problems of Doppler code and navigation data bit sign transition is the Improved Semi-bit Compensation (ISBC) acquisition method. This paper has implemented this method in the FPGA platform. In addition, due to the multiplicity of signal processing steps in GPS receivers, this paper has achieved an improvement in implementation by simplifying its design and implementation steps, compared to the previous methods, and with the minimum SNR value of -43.3dB, it has been able to successfully pay for the acquisition of at least four satellites.

In GPS receivers, due to the structure of the transmitted signal and the influence of physical factors on it, which greatly reduces the received signal power, different blocks are used to extract and retrieve satellite data. The first two blocks are called the acquisition block and the tracking block, respectively. The acquisition block operates to simplify the estimation of Doppler frequency and the code phase, and the tracking block performs the tracking of the satellite signal to extract the navigation data. Locked the PLL and DLL loops of this block on the received signal under critical conditions such as weak signal, accelerated movement, etc. is very important. Therefore, in cases where the loops open and lose the Doppler frequency and phase code of the received signal, depending on the capabilities embedded in the block, the duration of the loops being re-closed is one of the special privileges for this block. This paper deals with hardware implementation of FPGA-based optimized tracking block and evaluates the speed of closing the loops in the block and following the signal with the practical implementation of the hardware.