Design of 16- bit Approximate Multiplier with Digital Processing Application

The multipliers are important blocks that used in digital processing modern systems. So, design of the efficient multiplier is important advantage for digitally computational system. In some processing fields as the signal processing, the specified level of the error is acceptable, so used of accurate multiplier in the all of the processing fields is not essential. One of the important blocks of the multiplier is the compressor that is used in stage of the partial multiplication for decreasing operations. In this paper, new design of the 5:3 and 15:4 approximate compressors are proposed, the power consumption, propagation delay and error distance of proposed compressors in the comparison others have proper operating, with used of the proposed approximate compressors designed the approximate 16*16-bit multiplier. The overall of the proposed approximate multiplier is simulated and implemented by 180 nm CMOS technology and 1.8 V power supply by the Cadence tools. The result of simulation is shown that propagation delay proposed 5:3 compressors is 0.76 ns and power consumption is 0.935 μW with ±2 error distance. And also, the proposed 15:4 compressor has 1.12 ns propagation delay, 4.75 μW power consumption.