نشریه تحقیقات نوین در سیستم های قدرت هوشمند
سال نهم شماره 2 (پیاپی 22، تابستان 1399)

Power capacitors are important equipment of the power systems that are being operated in high voltage levels at high temperatures for long periods. As time goes on, their insulation fracture rate increases, and partial discharge is the most important cause of their fracture. Therefore, fast and accurate methods have great importance to accurately diagnosis the partial discharge. Conventional methods often require multiple sensors and signal parameters, which in turn increases the cost and complexity of the system. In this paper, extension neural network algorithm and synchronous detection based chaos theory is proposed to estimate the partial discharge level of power capacitors. This method uses an error diagnosis system for the power capacitor and extracts the properties of the properties by the synchronous detection based chaos theory method. The prominent advantage of this method is effective compression of the mass data and extracts the feature data to enhance the accuracy of the extension neural network method. The results show that the ENN diagnosis rate was 90% higher than the multi-layer method (79%) and the extension method shows 70% lower diagnosis rate.

As the power system restructured, new entities emerged in the electricity market, including retail electricity companies. These entities purchase electricity from the wholesale market and sell it to consumers at competitive pricing rate. With the intermediary role of these entities, it is important to adopt a proper strategy in dealing with supply and demand side because this proper strategy has a significant impact on profit or loss of the retailer. This paper presents a model to maximize the retailer profit while calculating the optimal risk limitation based on bilateral contracts, pool market, customer’s behavior and price elasticity of demand. The proposed model in the form of optimization problem solved as a nonlinear programming with SNOPT solver of GAMS software. The results of applying the proposed model show the accuracy of the results and maximize the retailer's profit in comparison with the basic model.

Nowadays, distributed generation (DG) is widely used in power systems. However, the use of DGs has caused new challenges in different aspects of power system operation, one of which is the effect of DGs on the optimal load shedding. Load shedding is a remedial action triggered after disturbances such line tripping. In fact, due to the line outage, the power flowing through other lines will increase which may cause protection systems to operate to trip the overloaded lines and in severe cases result in the system collapse. In this paper, a general load shedding method is proposed to prohibit the system from moving toward collapsing and helping the system to restore in the presence of DGs. In the proposed method, firstly the most critical line whose outage leads to the minimum values of stability indices is determined. Then, after putting this line out of service, harmony search algorithm is used to find the minimum amount of load shedding as well as the optimal location of DGs so that the loadability of the system is maximized preventing the system to collapse. The efficacy of the proposed methodology is demonstrated through applying it on IEEE 14 and 30-bus systems using various scenarios.

Renewable sources are used to provide power in power systems on feeders or near consumers. The placement and installation of these resources should take into account their negative effects on the distribution network. In this paper based on flow control of dispersed production resources by using current-voltage-voltage diagrams during the error, a method of regulating the coordination of protective measures is presented. The flows during the error, with the presence and absence of dispersed production resources, have been designated at various locations and compared to each other. The simulation results in ETAP software shown that adjust the coordination of protective equipment in some cases by entering these resources into the network, they get into trouble and the protective coordination is restored using the proposed method.

Power switches are designed to cut off normal currents and short circuit. They act like large switches that can be opened or closed by local switches or telecommunication signals by the remote protection system. Therefore, the protection of equipment and devices of the power system against defects and connections is done by the power switch. In this regard, the transient states caused by the opening and closing of the power switches in the compensated lines with series capacitors It is great in designing and coordinating insulation and protection systems. Therefore, in this paper, first the types of power switches are introduced and examined, and then the function of power switches when switching on compensated transmission lines with series capacitor with and without the presence of protection system is simulated. Also, transient overvoltage due to switching on such lines are investigated. The simulation results indicate the need for a protection system for series capacitors at the time of switching.

In microelectronic applications, the enhancement and scaling to the nanometer technology has caused the SRAM memories to be used as one of the basic and essential components in wireless communications in high performance server processors, multimedia applications and Systems On-Chip (SoC). In the recent years, different SRAM cells have been designed and the 6T-SRAM structure is the most commonly used. However, the supply voltage variations and disconnection may eliminate the stored data. The Memristor is invented as one of the mostly used nano-devices, it can solve the problem due to the fast switching speed, high endurance and data retention, low power consumption, high integration density and CMOS compatibility. In this thesis, two novels high-performance non-volatile SRAM cell using the CMOS-Memristor technique for SRAM memory array are proposed. In the first design, SRAM has eight MOSFETs and two Memristors (8T2M-SRAM) and in the second design, SRAM has nine MOSFETs and two Memristors (9T2M-SRAM). The proposed SRAM cells are designed using 0.18µm CMOS TSMC Technology at 1.8v supply voltage. The design strategy is to reduce the power consumption, improve the Static Noise Margin (SNM) in the design of the non-volatile SRAM cell over the previous cell. The results show, write '0' and write '1' dynamic power consumption the 8T2MSRAM cell has a 10% improvement over the 6T-SRAM. Also, there is a 54% improvement in the dynamic power consumption the 9T2M-SRAM cell in the read '0' mode and a 71% improvement in the read '1' mode. It is worth noting that the simulations are performed in HSPICE.