Nested Loops Tiling Considering Data Locality for Parallel Execution on Multi-core Processors

Recently, microprocessor industry has moved toward multi-core processor design and implementation. These high performance computing platforms have two important aspects: multiple computational cores and a hierarchy of cache. In order to use these platforms to speedup programs, there should be compiler techniques which consider these two aspects, simultaneously. An appropriate compiler technique is iteration space tiling, which is applied to obtain coarse grain parallelization as well as improving data locality in the nested loops on the multiprocessors. The problem is considering the loop parallelization and the data locality improvement, simultaneously. In this paper, a novel method for tile scheduling is presented in order to obtain parallel tiles based on the data reuse amongst them. Based on the proposed method, the data locality improvement according to the cache hierarchy along with the coarse grain parallelization is obtained.