Twin Microprocessors to Defend Side Channel Attack

A Side Channel Attacker tries to infer sensitive information from a security device like a smart card using its power consumption, timing information or electromagnetic emanation. Implementation of cryptographic algorithms, regardless of how much their security is mathematically proven, demand for extra considerations to be secure against SCA. In this paper we introduce a CPU architecture which can execute two queues of instructions randomly interleaved which together comprise a whole cryptographic algorithm. Since execution order of instructions varies from each run to another, power consumption pattern of device is undetermined and can resist against SCA. We also use a set of methods to develop a compiler toolkit which can accept a program and produce two queues of instructions equivalent two the original program. We examined strength of our method, conducting a Correlation Power Analysis which is one kind of SCA.