A low-power low-noise logarithmic amplifier for bio-potential signal recording applications

In this paper a low-power, low-noise logarithmic amplifier is presented in order to use in the front-end of bio-potential recording microsystems. To avoid increasing the temperature and so destruction of the surrounding tissue, low-power performance is critical. The logarithmic characteristic is obtained by using the piece-wise linear approximation and the parallel summation topology. This structure is capable to generate both current and voltage outputs. The offset cancellation mechanism in the feedback loop has been employed to remove the DC offset. The amplifier has been simulated in a 0.18 µm CMOS process. Implementation of the circuit is done by drawing the layout. The post simulation results demonstrate a CMRR of 130.2 dB at 50/60 Hz and an input referred noise of 3.22 µVrms in a band width of 0.1-10kHz. The power consumption is 3.96 µW from a 1.2 V power supply.