A CAD tool for design and optimizing latch comparators

In this paper, a CAD tool based on the link between Hspice and a heuristic algorithm called Inclined Planes Optimization (IPO) is provided, which its goal is to obtain an optimal design for voltage comparators. This tool uses detailed models of transistors and considers all parasitic elements, to achieve solutions close to reality. The proposed CAD tool minimizes a multi-objective function and provides several 2-dimensional Pareto-fronts. Therefore, the designer understands the correlation between objective functions and selects the optimal design considering the application requirements. To evaluate the final results, 1000-run of Monte Carlo simulation and PVT verification design is performed.